From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
To: <rkrcmar@redhat.com>, <joro@8bytes.org>, <pbonzini@redhat.com>,
<alex.williamson@redhat.com>
Cc: <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sherry.hurwitz@amd.com>,
Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Subject: [PART2 PATCH v6 09/12] iommu/amd: Enable vAPIC interrupt remapping mode by default
Date: Thu, 18 Aug 2016 14:42:41 -0500 [thread overview]
Message-ID: <1471549364-6672-10-git-send-email-Suravee.Suthikulpanit@amd.com> (raw)
In-Reply-To: <1471549364-6672-1-git-send-email-Suravee.Suthikulpanit@amd.com>
Introduce struct iommu_dev_data.use_vapic flag, which IOMMU driver
uses to determine if it should enable vAPIC support, by setting
the ga_mode bit in the device's interrupt remapping table entry.
Currently, it is enabled for all pass-through device if vAPIC mode
is enabled.
Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
---
drivers/iommu/amd_iommu.c | 44 +++++++++++++++++++++++++++++++++--------
drivers/iommu/amd_iommu_init.c | 12 ++++++++++-
drivers/iommu/amd_iommu_types.h | 2 +-
3 files changed, 48 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 65cdfcd..9cfac8b 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -105,6 +105,7 @@ struct iommu_dev_data {
bool pri_tlp; /* PASID TLB required for
PPR completions */
u32 errata; /* Bitmap for errata to apply */
+ bool use_vapic; /* Enable device to use vapic mode */
};
/*
@@ -3211,6 +3212,12 @@ static void amd_iommu_detach_device(struct iommu_domain *dom,
if (!iommu)
return;
+#ifdef CONFIG_IRQ_REMAP
+ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
+ (dom->type == IOMMU_DOMAIN_UNMANAGED))
+ dev_data->use_vapic = 0;
+#endif
+
iommu_completion_wait(iommu);
}
@@ -3236,6 +3243,15 @@ static int amd_iommu_attach_device(struct iommu_domain *dom,
ret = attach_device(dev, domain);
+#ifdef CONFIG_IRQ_REMAP
+ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
+ if (dom->type == IOMMU_DOMAIN_UNMANAGED)
+ dev_data->use_vapic = 1;
+ else
+ dev_data->use_vapic = 0;
+ }
+#endif
+
iommu_completion_wait(iommu);
return ret;
@@ -3986,7 +4002,7 @@ static void free_irte(u16 devid, int index)
static void irte_prepare(void *entry,
u32 delivery_mode, u32 dest_mode,
- u8 vector, u32 dest_apicid)
+ u8 vector, u32 dest_apicid, int devid)
{
union irte *irte = (union irte *) entry;
@@ -4000,13 +4016,14 @@ static void irte_prepare(void *entry,
static void irte_ga_prepare(void *entry,
u32 delivery_mode, u32 dest_mode,
- u8 vector, u32 dest_apicid)
+ u8 vector, u32 dest_apicid, int devid)
{
struct irte_ga *irte = (struct irte_ga *) entry;
+ struct iommu_dev_data *dev_data = search_dev_data(devid);
irte->lo.val = 0;
irte->hi.val = 0;
- irte->lo.fields_remap.guest_mode = 0;
+ irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0;
irte->lo.fields_remap.int_type = delivery_mode;
irte->lo.fields_remap.dm = dest_mode;
irte->hi.fields.vector = vector;
@@ -4060,11 +4077,14 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
u8 vector, u32 dest_apicid)
{
struct irte_ga *irte = (struct irte_ga *) entry;
+ struct iommu_dev_data *dev_data = search_dev_data(devid);
- irte->hi.fields.vector = vector;
- irte->lo.fields_remap.destination = dest_apicid;
- irte->lo.fields_remap.guest_mode = 0;
- modify_irte_ga(devid, index, irte, NULL);
+ if (!dev_data || !dev_data->use_vapic) {
+ irte->hi.fields.vector = vector;
+ irte->lo.fields_remap.destination = dest_apicid;
+ irte->lo.fields_remap.guest_mode = 0;
+ modify_irte_ga(devid, index, irte, NULL);
+ }
}
#define IRTE_ALLOCATED (~1U)
@@ -4207,7 +4227,7 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data,
data->irq_2_irte.index = index + sub_handle;
iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
apic->irq_dest_mode, irq_cfg->vector,
- irq_cfg->dest_apicid);
+ irq_cfg->dest_apicid, devid);
switch (info->type) {
case X86_IRQ_ALLOC_TYPE_IOAPIC:
@@ -4407,6 +4427,14 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
struct amd_ir_data *ir_data = data->chip_data;
struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
+ struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
+
+ /* Note:
+ * This device has never been set up for guest mode.
+ * we should not modify the IRTE
+ */
+ if (!dev_data || !dev_data->use_vapic)
+ return 0;
pi_data->ir_data = ir_data;
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 156ab4b..cd17136 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -146,7 +146,7 @@ struct ivmd_header {
bool amd_iommu_dump;
bool amd_iommu_irq_remap __read_mostly;
-int amd_iommu_guest_ir;
+int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
static bool amd_iommu_detected;
static bool __initdata amd_iommu_disabled;
@@ -2019,6 +2019,11 @@ static void early_enable_iommus(void)
iommu_enable(iommu);
iommu_flush_all_caches(iommu);
}
+
+#ifdef CONFIG_IRQ_REMAP
+ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
+ amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
+#endif
}
static void enable_iommus_v2(void)
@@ -2044,6 +2049,11 @@ static void disable_iommus(void)
for_each_iommu(iommu)
iommu_disable(iommu);
+
+#ifdef CONFIG_IRQ_REMAP
+ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
+ amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
+#endif
}
/*
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 71d1d0e..596e43f 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -803,7 +803,7 @@ struct irte_ga {
};
struct amd_irte_ops {
- void (*prepare)(void *, u32, u32, u8, u32);
+ void (*prepare)(void *, u32, u32, u8, u32, int);
void (*activate)(void *, u16, u16);
void (*deactivate)(void *, u16, u16);
void (*set_affinity)(void *, u16, u16, u8, u32);
--
1.9.1
next prev parent reply other threads:[~2016-08-19 1:19 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-18 19:42 [PART2 PATCH v6 00/12] iommu/AMD: Introduce IOMMU AVIC support Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 01/12] iommu/amd: Detect and enable guest vAPIC support Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 02/12] iommu/amd: Move and introduce new IRTE-related unions and structures Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 03/12] iommu/amd: Introduce interrupt remapping ops structure Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 04/12] iommu/amd: Add support for multiple IRTE formats Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 05/12] iommu/amd: Detect and initialize guest vAPIC log Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 06/12] iommu/amd: Adding GALOG interrupt handler Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 07/12] iommu/amd: Introduce amd_iommu_update_ga() Suravee Suthikulpanit
2016-08-22 5:50 ` kbuild test robot
2016-08-18 19:42 ` [PART2 PATCH v6 08/12] iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pass-through devices Suravee Suthikulpanit
2016-08-18 19:42 ` Suravee Suthikulpanit [this message]
2016-08-18 19:42 ` [PART2 PATCH v6 10/12] svm: Introduces AVIC per-VM ID Suravee Suthikulpanit
2016-08-19 13:26 ` Radim Krčmář
2016-08-18 19:42 ` [PART2 PATCH v6 11/12] svm: Introduce AMD IOMMU avic_ga_log_notifier Suravee Suthikulpanit
2016-08-18 19:42 ` [PART2 PATCH v6 12/12] svm: Implements update_pi_irte hook to setup posted interrupt Suravee Suthikulpanit
2016-08-19 14:49 ` Radim Krčmář
2016-08-19 15:04 ` Radim Krčmář
2016-08-22 9:19 ` Suravee Suthikulpanit
2016-08-22 10:09 ` Suravee Suthikulpanit
2016-08-22 15:16 ` Radim Krčmář
2016-08-23 10:51 ` kbuild test robot
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