From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 230B9C43214 for ; Mon, 9 Aug 2021 04:39:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED4596101D for ; Mon, 9 Aug 2021 04:39:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233013AbhHIEj0 (ORCPT ); Mon, 9 Aug 2021 00:39:26 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:32782 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbhHIEjZ (ORCPT ); Mon, 9 Aug 2021 00:39:25 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1794cvPi053042; Sun, 8 Aug 2021 23:38:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1628483937; bh=hMEiItd4QIo4kUch+Bv4wxFa1pGf9jYfLXOUQKMNT9c=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Ya6hTTCh6Z7M+W/aQX7PqEmbNqGEx6NYfAWn1NIiZsMUiLRt4foKZqYuHG59j5RDx j2m8vmxGanp/w6jEORH1KCAfIfTzcuiXDuEpJhxcbycnFWxJoC9Z9gl+RK7nrCr9DM rXiMX/KLjYevkasV/uODWhOkrNN1TIkSRf9F43NQ= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1794cvLJ067738 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 8 Aug 2021 23:38:57 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 8 Aug 2021 23:38:57 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Sun, 8 Aug 2021 23:38:57 -0500 Received: from [10.250.235.70] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1794crVI008485; Sun, 8 Aug 2021 23:38:53 -0500 Subject: Re: [PATCH v2 1/3] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts To: Marc Zyngier CC: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Tom Joseph , , , , , , Lokesh Vutla References: <20210804132912.30685-1-kishon@ti.com> <20210804132912.30685-2-kishon@ti.com> <87im0lw8qy.wl-maz@kernel.org> From: Kishon Vijay Abraham I Message-ID: <14717d53-1727-509c-9a62-02c1e8c5736e@ti.com> Date: Mon, 9 Aug 2021 10:08:47 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <87im0lw8qy.wl-maz@kernel.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 04/08/21 8:35 pm, Marc Zyngier wrote: > On Wed, 04 Aug 2021 14:29:10 +0100, > Kishon Vijay Abraham I wrote: >> >> Add bindings to specify interrupt controller for legacy interrupts. >> >> Signed-off-by: Kishon Vijay Abraham I >> --- >> .../bindings/pci/ti,j721e-pci-host.yaml | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml >> index cc900202df29..f461d7b4c0cc 100644 >> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml >> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml >> @@ -74,6 +74,11 @@ properties: >> >> msi-map: true >> >> +patternProperties: >> + "interrupt-controller": >> + type: object >> + description: interrupt controller to handle legacy interrupts. >> + >> required: >> - compatible >> - reg >> @@ -97,6 +102,8 @@ unevaluatedProperties: false >> >> examples: >> - | >> + #include >> + #include >> #include >> #include >> >> @@ -131,5 +138,13 @@ examples: >> ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, >> <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; >> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >> + >> + >> + pcie0_intc: interrupt-controller { >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + interrupt-parent = <&gic500>; >> + interrupts = ; > > Are you sure about the edge signalling? How is the interrupt > retriggered when the input is still high, which could well be the case > for shared INTx? There is a EOI register which is used for re-triggering the interrupt. That functionality is broken in J721E but is fixed in J7200 (the following two patches in the series deals with that). Thanks, Kishon