From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161543AbcHaR56 (ORCPT ); Wed, 31 Aug 2016 13:57:58 -0400 Received: from mail-eopbgr30128.outbound.protection.outlook.com ([40.107.3.128]:22896 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1161225AbcHaR5v (ORCPT ); Wed, 31 Aug 2016 13:57:51 -0400 X-Greylist: delayed 69762 seconds by postgrey-1.27 at vger.kernel.org; Wed, 31 Aug 2016 13:57:50 EDT From: Marcel Ziswiler To: "jonathanh@nvidia.com" , "mirza.krak@gmail.com" , "swarren@wwwdotorg.org" , "thierry.reding@gmail.com" CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "mturquette@baylibre.com" , "pgaikwad@nvidia.com" , "linux@armlinux.org.uk" , "devicetree@vger.kernel.org" , "gnurou@gmail.com" , "mark.rutland@arm.com" , "linux-arm-kernel@lists.infradead.org" , "pdeschrijver@nvidia.com" , "sboyd@codeaurora.org" , "linux-tegra@vger.kernel.org" , "linux-clk@vger.kernel.org" Subject: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Thread-Topic: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Thread-Index: AQHSA1d98ujtJjBPR0ydcsViq/bvhA== Date: Wed, 31 Aug 2016 07:15:45 +0000 Message-ID: <1472627744.31008.2.camel@toradex.com> References: <1472569308.5703.22.camel@toradex.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=marcel.ziswiler@toradex.com; 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spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" Content-ID: <4351CFD673638B43885E377849671178@eurprd05.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2016 07:15:45.4395 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB1884 X-Microsoft-Exchange-Diagnostics: 1;HE1PR05MB1884;23:8kkmTU0GXtOFNEw79A/8wk5E2XAP+/tWc37N2QbLugdGdLM3qbCrtMeSr0+liPZcafvibPUOOAeZXArj0CW6Itap8QHzE+41akD4OEJZDwrBRVhTaPDkP596JMupJpyJAV0llWTs0YcRQJcZB9p7UJThHwUaMvvmQ2Xzdsh6940th3p2nAvISg5xoANTnhOX X-OriginatorOrg: toradex.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u7VHw9J1006850 On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: > > From: Mirza Krak > > Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz > which > is max rate. table > > Signed-off-by: Mirza Krak mane.org> > --- > Changes in v2: > - no changes > >  drivers/clk/tegra/clk-tegra20.c | 1 + >  1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk- > tegra20.c > index 837e5cb..13d3b5a 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] > __initdata = { >   { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, >   { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, >   { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, > + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 }, I'm just curious where that 92 MHz came from. According to the Tegra 2 Interface Design Guide up to 133 MHz should actually be possible. > >   { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, >   { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, >   { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, > -- > 2.1.4