From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760329AbcHaTcT (ORCPT ); Wed, 31 Aug 2016 15:32:19 -0400 Received: from realmta2.virtu.nl ([217.114.99.37]:45371 "EHLO realmta2.virtu.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760221AbcHaTcQ (ORCPT ); Wed, 31 Aug 2016 15:32:16 -0400 From: jorik@kippendief.biz To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Jorik Jonker Subject: [PATCH v2 3/7] dts: sun8i-h3: add i2c0/i2c1 SoC peripherals Date: Wed, 31 Aug 2016 21:30:54 +0200 Message-Id: <1472671858-29220-4-git-send-email-jorik@kippendief.biz> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472671858-29220-1-git-send-email-jorik@kippendief.biz> References: <1472671858-29220-1-git-send-email-jorik@kippendief.biz> X-Virtu-SpamScore: - Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jorik Jonker This enables the i2c0/i2c1 peripherals of the SoC. There is actually a third controller, but I do not have a board on hands on which i2c2 is exposed in such a way that I can verify that it works. Signed-off-by: Jorik Jonker --- arch/arm/boot/dts/sun8i-h3.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 0637b95..b4ce925 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -469,6 +469,28 @@ status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- 2.7.4