From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760368AbcJ1NuE (ORCPT ); Fri, 28 Oct 2016 09:50:04 -0400 Received: from mga14.intel.com ([192.55.52.115]:62298 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756563AbcJ1NuD (ORCPT ); Fri, 28 Oct 2016 09:50:03 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,410,1473145200"; d="scan'208";a="1077215833" From: Grzegorz Andrejczuk To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org Cc: bp@suse.de, dave.hansen@linux.intel.com, lukasz.daniluk@intel.com, james.h.cownie@intel.com, jacob.jun.pan@intel.com, Piotr.Luc@intel.com, linux-kernel@vger.kernel.org, Grzegorz Andrejczuk Subject: [PATCH v7 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Date: Fri, 28 Oct 2016 15:49:51 +0200 Message-Id: <1477662595-21011-1-git-send-email-grzegorz.andrejczuk@intel.com> X-Mailer: git-send-email 2.5.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs. Then expose it as CPU feature and introduces elf HWCAP capability for x86. Reference: https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait v7: Change order of the patches, with this code looks cleaner. Changed the name of MSR to MSR_MISC_FEATURE_ENABLES. Used Word 3 25th bit to expose feature. v6: v5: When phir3mwait=disable is cmdline switch off r3 mwait feature Fix typos v4: Wrapped the enabling code by CONFIG_X86_64 Add documentation for phir3mwait=disable cmdline switch Move probe_ function call from early_intel_init to intel_init Fixed commit messages v3: Included Daves and Thomas comments v2: Check MSR before wrmsrl Shortened names Used Word 3 for feature init_scattered_cpuid_features() Fixed commit messages Grzegorz Andrejczuk (4): x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT x86/cpufeature: Add PHIR3MWAIT to CPU features x86: Add enabling of the R3MWAIT during boot Documentation/kernel-parameters.txt | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/elf.h | 9 ++++++++ arch/x86/include/asm/msr-index.h | 5 +++++ arch/x86/include/uapi/asm/hwcap2.h | 7 ++++++ arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/cpu/intel.c | 43 +++++++++++++++++++++++++++++++++++++ 7 files changed, 73 insertions(+) create mode 100644 arch/x86/include/uapi/asm/hwcap2.h -- 2.5.1