From: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org
Cc: bp@suse.de, dave.hansen@linux.intel.com,
lukasz.daniluk@intel.com, james.h.cownie@intel.com,
jacob.jun.pan@intel.com, Piotr.Luc@intel.com,
linux-kernel@vger.kernel.org,
Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Subject: [PATCH v7 1/4] x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h
Date: Fri, 28 Oct 2016 15:49:52 +0200 [thread overview]
Message-ID: <1477662595-21011-2-git-send-email-grzegorz.andrejczuk@intel.com> (raw)
In-Reply-To: <1477662595-21011-1-git-send-email-grzegorz.andrejczuk@intel.com>
Intel Xeon Phi x200 (codenamed Knights Landing) has MSR
MISC_FEATURE_ENABLES 0x140.
Setting 2nd bit of this register makes MONITOR and MWAIT instructions
do not cause invalid-opcode exception when called from ring different
than 0.
Hex Dec Name Scope
140H 320 MISC_FEATURE_ENABLES Thread
0 Reserved
1 if set to 1, the MONITOR and MWAIT instructions do not
cause invalid-opcode exceptions when executed with CPL > 0
or in virtual-8086 mode. If MWAIT is executed when CPL > 0
or in virtual-8086 mode, and if EAX indicates a C-state
other than C0 or C1, the instruction operates as if EAX
indicated the C-state C1.
63:2 Reserved
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/msr-index.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 56f4c66..0fc220d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -540,6 +540,11 @@
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
+/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
+#define MSR_MISC_FEATURE_ENABLES 0x00000140
+#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1
+#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
+
#define MSR_IA32_TSC_DEADLINE 0x000006E0
/* P4/Xeon+ specific */
--
2.5.1
next prev parent reply other threads:[~2016-10-28 13:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-28 13:49 [PATCH v7 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-10-28 13:49 ` Grzegorz Andrejczuk [this message]
2016-10-31 1:14 ` [PATCH v7 1/4] x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h Thomas Gleixner
2016-10-28 13:49 ` [PATCH v7 2/4] x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT Grzegorz Andrejczuk
2016-10-31 1:14 ` Thomas Gleixner
2016-10-28 13:49 ` [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
2016-10-31 1:15 ` Thomas Gleixner
2016-10-28 13:49 ` [PATCH v7 4/4] x86: Add enabling of the R3MWAIT during boot Grzegorz Andrejczuk
2016-10-31 1:15 ` Thomas Gleixner
2016-12-03 20:27 ` [PATCH v7 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Pavel Machek
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