From: Anurup M <anurupvasu@gmail.com>
To: anurup.m@huawei.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: will.deacon@arm.com, mark.rutland@arm.com,
zhangshaokun@hisilicon.com, xuwei5@hisilicon.com,
john.garry@huawei.com, gabriele.paoloni@huawei.com,
sanil.kumar@hisilicon.com, shyju.pv@huawei.com,
tanxiaojun@huawei.com, shiju.jose@huawei.com,
linuxarm@huawei.com
Subject: [PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Date: Wed, 2 Nov 2016 11:42:48 -0400 [thread overview]
Message-ID: <1478101374-18778-6-git-send-email-anurup.m@huawei.com> (raw)
In-Reply-To: <1478101374-18778-1-git-send-email-anurup.m@huawei.com>
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
.../devicetree/bindings/arm/hisilicon/pmu.txt | 127 +++++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
new file mode 100644
index 0000000..e7b35e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
@@ -0,0 +1,127 @@
+Hisilicon SoC hip05/06/07 ARMv8 PMU
+===================================
+
+The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
+system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR
+comtroller. These PMU devices are independent and have hardware logic to
+gather statistics and performance information.
+
+HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die
+is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
+is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
+e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
+
+The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.
+For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
+the parent node will be the djtag node of the corresponding CPU die(SCCL).
+
+For uncore PMU devices there are some common required properties as detailed
+below.
+
+Required properties:
+ - compatible : This field contain two values. The first value is
+ always "hisilicon" and second value is the Module type as shown
+ in below examples:
+ (a) "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
+ device (Version 1)
+ (b) "hisilicon,hisi-pmu-mn-v1" for Hisilicon SoC MN PMU
+ device (Version 1)
+ (c) "hisilicon,hisi-pmu-ddrc-v1" for Hisilicon SoC DDRC PMU
+ device (Version 1)
+ The hip05/06/07 chips have v1 hardware for L3C, MN and DDRC.
+
+ - scl-id : The Super Cluster ID. This can be the ID of the CPU die
+ or IO die in the chip.
+
+ - num-events : No of events supported by this PMU device.
+
+ - num-counters : No of hardware counters available for counting.
+
+L3 cache
+--------
+The L3 cache is dedicated for each SCCL and hence there are separate DT nodes
+for L3 cache for each SCCL. For L3 cache PMU the additional required properties
+are
+ - counter-reg : Counter register offset.
+
+ - evtype-reg : Event select register offset.
+
+ - evctrl-reg : Event counting control(LAUCTRL) register offset.
+
+ - event-en : Event enable value.
+
+ - module-id : Module ID to input for djtag. This property is an array of
+ module_id for each L3 cache banks.
+
+ - num-banks : Number of banks or instances of the device.
+
+ - cfgen-map : Config enable array to select the bank.
+
+Miscellaneous Node
+-------------------
+The MN is dedicated for each SCCL and hence there are separate DT nodes for MN
+for each SCCL. For MN PMU the additional required properties are
+ - counter-reg : Counter register offset.
+
+ - evtype-reg : Event select register offset.
+
+ - evctrl-reg : Event counting control register offset.
+
+ - module-id : Module ID to input for djtag. As MN doesnot have multiple banks
+ this property is a single value.
+
+ - cfgen-map : Config enable to select the bank. For MN it is a single value
+
+ - event-en : Event enable value.
+
+Example:
+
+ djtag0: djtag@0 {
+ compatible = "hisilicon,hip05-cpu-djtag-v1";
+ pmul3c0 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x02>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04 0x04 0x04 0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x1000000>;
+ evtype-reg = <0x140>;
+ };
+
+ pmumn0 {
+ compatible = "hisilicon,hisi-pmu-mn-v1";
+ scl-id = <0x02>;
+ num-events = <0x09>;
+ num-counters = <0x04>;
+ module-id = <0x0b>;
+ cfgen-map = <0x01>;
+ counter-reg = <0x30>;
+ evctrl-reg = <0x40>;
+ event-en = <0x01>;
+ evtype-reg = <0x48>;
+ };
+ };
+
+DDR controller
+--------------
+Each SCCL in Hip05/06/07 chips have 2 DDR channels and hence 2 DDR controllers.
+There are separate DT nodes for each DDR channel.
+For DDRC PMU the additional required properties are
+
+ - ch-id : DDRC Channel ID.
+ - reg : Register base address and range for the DDRC channel.
+
+Example:
+ /* DDRC for CPU die scl #2 Channel #1 for hip05 */
+ pmu_sccl0_ddrc1: pmu_ddrc1@80358000 {
+ compatible = "hisilicon,hisi-pmu-ddrc-v1";
+ scl-id = <0x02>;
+ ch-id = <0x1>;
+ num-events = <0x0D>;
+ num-counters = <0x04>;
+ reg = <0x80358000 0x10000>; /* TOTEMC DDRC1 */
+ };
--
2.1.4
next prev parent reply other threads:[~2016-11-02 15:44 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-02 15:42 [PATCH v1 00/11] perf: arm64: Support for Hisilicon SoC Hardware event counters Anurup M
2016-11-02 15:42 ` [PATCH v1 01/11] arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support Anurup M
2016-11-02 15:42 ` [PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings Anurup M
2016-11-02 15:42 ` [PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver Anurup M
2016-11-03 1:59 ` kbuild test robot
2016-11-07 13:26 ` Arnd Bergmann
2016-11-07 14:15 ` John Garry
2016-11-07 20:08 ` Arnd Bergmann
2016-11-08 11:23 ` John Garry
2016-11-08 11:45 ` Arnd Bergmann
2016-11-08 13:49 ` John Garry
2016-11-08 15:10 ` Arnd Bergmann
2016-11-08 15:17 ` John Garry
2016-11-09 10:44 ` Anurup M
2016-11-08 15:51 ` Anurup M
2016-11-09 9:06 ` John Garry
2016-11-11 10:35 ` Anurup M
2016-11-08 7:02 ` Tan Xiaojun
2016-11-08 7:38 ` Anurup M
2016-11-08 11:43 ` Arnd Bergmann
2016-11-08 13:46 ` Anurup M
2016-11-08 15:08 ` Arnd Bergmann
2016-11-09 4:28 ` Anurup M
2016-11-09 21:40 ` Arnd Bergmann
2016-11-11 10:23 ` Anurup M
2016-11-02 15:42 ` [PATCH v1 04/11] Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event counting Anurup M
2016-11-02 15:42 ` Anurup M [this message]
2016-11-02 15:42 ` [PATCH v1 06/11] perf: hisi: Update Kconfig for Hisilicon PMU support Anurup M
2016-11-02 15:42 ` [PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters Anurup M
2016-11-02 15:42 ` [PATCH v1 08/11] perf: hisi: Add sysfs attributes for L3 cache(L3C) PMU Anurup M
2016-11-02 15:42 ` [PATCH v1 09/11] perf: hisi: Miscellanous node(MN) event counting in perf Anurup M
2016-11-02 15:42 ` [PATCH v1 10/11] perf: hisi: Support for Hisilicon DDRC PMU Anurup M
2016-11-02 15:42 ` [PATCH v1 11/11] dts: arm64: hip06: Add Hisilicon SoC PMU support Anurup M
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