From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932736AbcKCQCQ (ORCPT ); Thu, 3 Nov 2016 12:02:16 -0400 Received: from mga04.intel.com ([192.55.52.120]:2012 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932533AbcKCQCP (ORCPT ); Thu, 3 Nov 2016 12:02:15 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,587,1473145200"; d="scan'208";a="27017961" From: Grzegorz Andrejczuk To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org Cc: bp@suse.de, dave.hansen@linux.intel.com, lukasz.daniluk@intel.com, james.h.cownie@intel.com, jacob.jun.pan@intel.com, Piotr.Luc@intel.com, linux-kernel@vger.kernel.org, Grzegorz Andrejczuk Subject: [PATCH v8 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Date: Thu, 3 Nov 2016 17:01:35 +0100 Message-Id: <1478188895-13001-1-git-send-email-grzegorz.andrejczuk@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <20161103145650.kl7glxcfatad5ium@pd.tnic> References: <20161103145650.kl7glxcfatad5ium@pd.tnic> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Intel Xeon Phi x200 (KnightsLanding) CPU feature - ring 3 MONITOR/MWAIT. Signed-off-by: Grzegorz Andrejczuk --- arch/x86/include/asm/cpufeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 92a8308..98414c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -100,7 +100,7 @@ #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ -/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ +#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ -- 2.5.1