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From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Noam Camus <noamca@mellanox.com>, <tglx@linutronix.de>,
	<linux-snps-arc@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <Alexey.Brodkin@synopsys.com>,
	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Subject: [PATCH v4 7/8] ARC: breakout timer include code into separate header ...
Date: Fri, 11 Nov 2016 13:38:51 -0800	[thread overview]
Message-ID: <1478900332-24279-8-git-send-email-vgupta@synopsys.com> (raw)
In-Reply-To: <1478900332-24279-1-git-send-email-vgupta@synopsys.com>

... which allows for use in drivers/clocksource later

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---
 arch/arc/include/asm/arcregs.h |  9 +--------
 arch/arc/kernel/time.c         | 18 +++---------------
 include/soc/arc/timers.h       | 38 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 23 deletions(-)
 create mode 100644 include/soc/arc/timers.h

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 7a2c36e83186..da41a54ea2d7 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -20,7 +20,6 @@
 #define ARC_REG_FP_V2_BCR	0xc8	/* ARCv2 FPU */
 #define ARC_REG_SLC_BCR		0xce
 #define ARC_REG_DCCM_BUILD	0x74	/* DCCM size (common) */
-#define ARC_REG_TIMERS_BCR	0x75
 #define ARC_REG_AP_BCR		0x76
 #define ARC_REG_ICCM_BUILD	0x78	/* ICCM size (common) */
 #define ARC_REG_XY_MEM_BCR	0x79
@@ -208,13 +207,7 @@ struct bcr_fp_arcv2 {
 #endif
 };
 
-struct bcr_timer {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-	unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
-#else
-	unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
-#endif
-};
+#include <soc/arc/timers.h>
 
 struct bcr_bpu_arcompact {
 #ifdef CONFIG_CPU_BIG_ENDIAN
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index ec1b896f27b2..94b9cd169374 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -38,22 +38,10 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <asm/irq.h>
-#include <asm/arcregs.h>
 
+#include <soc/arc/timers.h>
 #include <soc/arc/mcip.h>
 
-/* Timer related Aux registers */
-#define ARC_REG_TIMER0_LIMIT	0x23	/* timer 0 limit */
-#define ARC_REG_TIMER0_CTRL	0x22	/* timer 0 control */
-#define ARC_REG_TIMER0_CNT	0x21	/* timer 0 count */
-#define ARC_REG_TIMER1_LIMIT	0x102	/* timer 1 limit */
-#define ARC_REG_TIMER1_CTRL	0x101	/* timer 1 control */
-#define ARC_REG_TIMER1_CNT	0x100	/* timer 1 count */
-
-#define TIMER_CTRL_IE	(1 << 0) /* Interrupt when Count reaches limit */
-#define TIMER_CTRL_NH	(1 << 1) /* Count only when CPU NOT halted */
-
-#define ARC_TIMER_MAX	0xFFFFFFFF
 
 static unsigned long arc_timer_freq;
 
@@ -218,7 +206,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node)
 	if (ret)
 		return ret;
 
-	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
+	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
 	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
 	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
 
@@ -296,7 +284,7 @@ static int arc_timer_starting_cpu(unsigned int cpu)
 
 	evt->cpumask = cpumask_of(smp_processor_id());
 
-	clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX);
+	clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
 	enable_percpu_irq(arc_timer_irq, 0);
 	return 0;
 }
diff --git a/include/soc/arc/timers.h b/include/soc/arc/timers.h
new file mode 100644
index 000000000000..a20ed2fbc432
--- /dev/null
+++ b/include/soc/arc/timers.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_ARC_TIMERS_H
+#define __SOC_ARC_TIMERS_H
+
+#include <soc/arc/aux.h>
+
+/* Timer related Aux registers */
+#define ARC_REG_TIMER0_LIMIT	0x23	/* timer 0 limit */
+#define ARC_REG_TIMER0_CTRL	0x22	/* timer 0 control */
+#define ARC_REG_TIMER0_CNT	0x21	/* timer 0 count */
+#define ARC_REG_TIMER1_LIMIT	0x102	/* timer 1 limit */
+#define ARC_REG_TIMER1_CTRL	0x101	/* timer 1 control */
+#define ARC_REG_TIMER1_CNT	0x100	/* timer 1 count */
+
+/* CTRL reg bits */
+#define TIMER_CTRL_IE	        (1 << 0) /* Interrupt when Count reaches limit */
+#define TIMER_CTRL_NH	        (1 << 1) /* Count only when CPU NOT halted */
+
+#define ARC_TIMERN_MAX		0xFFFFFFFF
+
+#define ARC_REG_TIMERS_BCR	0x75
+
+struct bcr_timer {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
+#else
+	unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
+#endif
+};
+
+#endif
-- 
2.7.4

  parent reply	other threads:[~2016-11-11 21:39 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-11 21:38 [PATCH v4 0/8] Move ARC timer code into drivers/clocksource/ Vineet Gupta
2016-11-11 21:38 ` [PATCH v4 1/8] ARC: timer: gfrc, rtc: deuglify big endian code Vineet Gupta
2016-11-11 21:38 ` [PATCH v4 2/8] ARC: timer: gfrc, rtc: Read BCR to detect whether hardware exists Vineet Gupta
2016-11-11 21:38 ` [PATCH v4 3/8] ARC: time: move time_init() out of the driver Vineet Gupta
2016-11-11 21:38 ` [PATCH v4 4/8] ARC: timer: Build gfrc, rtc under same option (64-bit timers) Vineet Gupta
2016-11-11 21:38 ` [PATCH v4 5/8] ARC: breakout aux handling into a separate header Vineet Gupta
2016-11-11 21:38 ` [PATCH v4 6/8] ARC: move mcip.h into include/soc and adjust the includes Vineet Gupta
2016-11-11 21:38 ` Vineet Gupta [this message]
2016-11-11 21:38 ` [PATCH v4 8/8] clocksource: import ARC timer driver Vineet Gupta
2016-11-11 23:11   ` Daniel Lezcano
2016-11-12  0:53     ` Vineet Gupta
     [not found]       ` <CAKnoXLzY7Qxw39R029cprqzy4WvKXYf5PReutORO+JyMvaxeqA@mail.gmail.com>
2016-11-15 10:30         ` Daniel Lezcano
2016-11-15 17:16           ` Vineet Gupta
2016-11-15 17:23             ` Daniel Lezcano
2016-11-15 17:27               ` Vineet Gupta
     [not found]                 ` <DB6PR0501MB2518CBABEBEB7499F0D023A0AABF0@DB6PR0501MB2518.eurprd05.prod.outlook.com>
2016-11-15 17:49                   ` Daniel Lezcano
     [not found]                     ` <DB6PR0501MB25183F3E7B3B5D224F646F79AABF0@DB6PR0501MB2518.eurprd05.prod.outlook.com>
2016-11-15 19:29                       ` Daniel Lezcano

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