From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933270AbcK1Obx (ORCPT ); Mon, 28 Nov 2016 09:31:53 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:36721 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933126AbcK1Obh (ORCPT ); Mon, 28 Nov 2016 09:31:37 -0500 From: Alexander Kochetkov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Thomas Gleixner , Heiko Stuebner , Mark Rutland , Rob Herring , Russell King , Caesar Wang , Huang Tao , Daniel Lezcano , Alexander Kochetkov Subject: [PATCHv2 04/11] ARM: dts: rockchip: add timer entries to rk3188 dtsi Date: Mon, 28 Nov 2016 17:31:19 +0300 Message-Id: <1480343486-25539-5-git-send-email-al.kochet@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1480343486-25539-1-git-send-email-al.kochet@gmail.com> References: <1480343486-25539-1-git-send-email-al.kochet@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The patch add two timers to all rk3188 based boards. The first timer is from alive subsystem and it act as a backup for the local timers at sleep time. It act the same as timers on other rockchip chips already present in kernel. The second timer is from CPU subsystem and act as replacement for the arm-global-timer clocksource. It run as stable frequency 24MHz. Signed-off-by: Alexander Kochetkov --- arch/arm/boot/dts/rk3188.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 31f81b2..0dc52fe 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -106,6 +106,22 @@ }; }; + timer3: timer@2000e000 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x2000e000 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; + clock-names = "timer", "pclk"; + }; + + timer6: timer@200380a0 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x200380a0 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; -- 1.7.9.5