From: <gabriel.fernandez@st.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@armlinux.org.uk>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Nicolas Pitre <nico@linaro.org>, Arnd Bergmann <arnd@arndb.de>,
<daniel.thompson@linaro.org>, <andrea.merello@gmail.com>,
<radoslaw.pietrzyk@gmail.com>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<kernel@stlinux.com>, <gabriel.fernandez@st.com>,
<ludovic.barre@st.com>, <olivier.bideau@st.com>,
<amelie.delaunay@st.com>
Subject: [PATCH v4 7/9] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board
Date: Tue, 13 Dec 2016 15:20:18 +0100 [thread overview]
Message-ID: <1481638820-29324-8-git-send-email-gabriel.fernandez@st.com> (raw)
In-Reply-To: <1481638820-29324-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
from pll-sai-p.
The SDIO clock could be also derived from 48Mhz or from sys clock.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 46 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 2bff436..11174a5 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -211,7 +211,7 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
- { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
+ { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
{ STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
@@ -951,6 +951,10 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
"no-clock" };
+static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
+
+static const char *sdmux_parents[2] = { "pll48", "sys" };
+
struct stm32_aux_clk {
int idx;
const char *name;
@@ -1000,6 +1004,45 @@ struct stm32f4_clk_data {
},
};
+static const struct stm32_aux_clk stm32f469_aux_clk[] = {
+ {
+ CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
+ NO_MUX, 0, 0,
+ STM32F4_RCC_APB2ENR, 26,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
+ STM32F4_RCC_CFGR, 23, 1,
+ NO_GATE, 0,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
+ STM32F4_RCC_DCKCFGR, 20, 3,
+ STM32F4_RCC_APB2ENR, 22,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
+ STM32F4_RCC_DCKCFGR, 22, 3,
+ STM32F4_RCC_APB2ENR, 22,
+ CLK_SET_RATE_PARENT
+ },
+ {
+ NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
+ STM32F4_RCC_DCKCFGR, 27, 1,
+ NO_GATE, 0,
+ 0
+ },
+ {
+ NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
+ STM32F4_RCC_DCKCFGR, 28, 1,
+ NO_GATE, 0,
+ 0
+ },
+};
+
static const struct stm32f4_clk_data stm32f429_clk_data = {
.gates_data = stm32f429_gates,
.gates_map = stm32f42xx_gate_map,
@@ -1014,8 +1057,8 @@ struct stm32f4_clk_data {
.gates_map = stm32f46xx_gate_map,
.gates_num = ARRAY_SIZE(stm32f469_gates),
.pll_data = stm32f469_pll,
- .aux_clk = stm32f429_aux_clk,
- .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
+ .aux_clk = stm32f469_aux_clk,
+ .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
};
static const struct of_device_id stm32f4_of_match[] = {
--
1.9.1
next prev parent reply other threads:[~2016-12-13 14:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 14:20 [PATCH v4 0/9] STM32F4 missing clocks gabriel.fernandez
2016-12-13 14:20 ` [PATCH v4 1/9] clk: stm32f4: Update DT bindings documentation gabriel.fernandez
2016-12-22 0:10 ` Stephen Boyd
2017-01-09 16:28 ` Alexandre Torgue
2017-01-09 19:33 ` Stephen Boyd
2017-01-10 10:08 ` Alexandre Torgue
2016-12-13 14:20 ` [PATCH v4 2/9] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards gabriel.fernandez
2016-12-22 0:10 ` Stephen Boyd
2016-12-13 14:20 ` [PATCH v4 3/9] clk: stm32f4: Add post divisor for I2S & SAI PLLs gabriel.fernandez
2016-12-22 0:11 ` Stephen Boyd
2016-12-13 14:20 ` [PATCH v4 4/9] clk: stm32f4: Add lcd-tft clock gabriel.fernandez
2016-12-22 0:11 ` Stephen Boyd
2016-12-13 14:20 ` [PATCH v4 5/9] clk: stm32f4: Add I2S clock gabriel.fernandez
2016-12-22 0:11 ` Stephen Boyd
2016-12-13 14:20 ` [PATCH v4 6/9] clk: stm32f4: Add SAI clocks gabriel.fernandez
2016-12-22 0:11 ` Stephen Boyd
2016-12-13 14:20 ` gabriel.fernandez [this message]
2016-12-22 0:11 ` [PATCH v4 7/9] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board Stephen Boyd
2016-12-13 14:20 ` [PATCH v4 8/9] ARM: dts: stm32f4: Add external I2S clock gabriel.fernandez
2017-01-10 10:59 ` Alexandre Torgue
2016-12-13 14:20 ` [PATCH v4 9/9] ARM: dts: stm32f4: Include auxiliary stm32fx clock definition gabriel.fernandez
2017-01-10 10:59 ` Alexandre Torgue
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1481638820-29324-8-git-send-email-gabriel.fernandez@st.com \
--to=gabriel.fernandez@st.com \
--cc=alexandre.torgue@st.com \
--cc=amelie.delaunay@st.com \
--cc=andrea.merello@gmail.com \
--cc=arnd@arndb.de \
--cc=daniel.thompson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=kernel@stlinux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=ludovic.barre@st.com \
--cc=mark.rutland@arm.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=mturquette@baylibre.com \
--cc=nico@linaro.org \
--cc=olivier.bideau@st.com \
--cc=radoslaw.pietrzyk@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).