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From: Liang Li <liang.z.li@intel.com>
To: kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, tglx@linutronix.de,
	mingo@redhat.com, kirill.shutemov@linux.intel.com,
	dave.hansen@linux.intel.com, guangrong.xiao@linux.intel.com,
	pbonzini@redhat.com, rkrcmar@redhat.com,
	Liang Li <liang.z.li@intel.com>
Subject: [PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table
Date: Thu, 29 Dec 2016 17:26:00 +0800	[thread overview]
Message-ID: <1483003563-25847-2-git-send-email-liang.z.li@intel.com> (raw)
In-Reply-To: <1483003563-25847-1-git-send-email-liang.z.li@intel.com>

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Define the related bits for the 5 level page table, which supports
57 bits width virtual address space. This patch maybe included in
Kirill's patch set which enables 5 level page table for x86,
because 5 level EPT doesn't depend on 5 level page table, we put
it here for independence.

Signed-off-by: Liang Li <liang.z.li@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
---
 arch/x86/include/asm/cpufeatures.h          | 1 +
 arch/x86/include/uapi/asm/processor-flags.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee31..2cf4018 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -288,6 +288,7 @@
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_LA57	(16*32 + 16) /* 5-level page tables */
 #define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h
index 567de50..185f3d1 100644
--- a/arch/x86/include/uapi/asm/processor-flags.h
+++ b/arch/x86/include/uapi/asm/processor-flags.h
@@ -104,6 +104,8 @@
 #define X86_CR4_OSFXSR		_BITUL(X86_CR4_OSFXSR_BIT)
 #define X86_CR4_OSXMMEXCPT_BIT	10 /* enable unmasked SSE exceptions */
 #define X86_CR4_OSXMMEXCPT	_BITUL(X86_CR4_OSXMMEXCPT_BIT)
+#define X86_CR4_LA57_BIT	12 /* enable 5-level page tables */
+#define X86_CR4_LA57		_BITUL(X86_CR4_LA57_BIT)
 #define X86_CR4_VMXE_BIT	13 /* enable VMX virtualization */
 #define X86_CR4_VMXE		_BITUL(X86_CR4_VMXE_BIT)
 #define X86_CR4_SMXE_BIT	14 /* enable safer mode (TXT) */
-- 
1.9.1

  reply	other threads:[~2016-12-29  9:32 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-29  9:25 [PATCH RFC 0/4] 5-level EPT Liang Li
2016-12-29  9:26 ` Liang Li [this message]
2016-12-29  9:26 ` [PATCH RFC 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Liang Li
2017-03-09 14:39   ` Paolo Bonzini
2016-12-29  9:26 ` [PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support Liang Li
2017-03-09 15:12   ` Paolo Bonzini
2016-12-29  9:26 ` [PATCH RFC 4/4] VMX: Expose the LA57 feature to VM Liang Li
2017-03-09 15:16   ` Paolo Bonzini
2016-12-29 20:38 ` [PATCH RFC 0/4] 5-level EPT Valdis.Kletnieks
2016-12-30  1:26   ` Li, Liang Z
2017-01-02 10:18 ` Paolo Bonzini
2017-01-17  2:18   ` Li, Liang Z
2017-03-09 14:16     ` Paolo Bonzini
2017-03-10  8:00       ` Yu Zhang
2017-01-05 13:26 ` Kirill A. Shutemov

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