From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, mark.rutland@arm.com, dave.martin@arm.com,
aph@redhat.com, ryan.arnold@linaro.org,
adhemerval.zanella@linaro.org, sid@reserved-bit.com,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v3 6/9] arm64: Add helper to decode register from instruction
Date: Wed, 4 Jan 2017 17:49:04 +0000 [thread overview]
Message-ID: <1483552147-9605-7-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1483552147-9605-1-git-send-email-suzuki.poulose@arm.com>
Add a helper to extract the register field from a given
instruction.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/insn.h | 2 ++
arch/arm64/kernel/insn.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index bc85366..aecc07e 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -332,6 +332,8 @@ bool aarch64_insn_is_branch(u32 insn);
u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
u32 insn, u64 imm);
+u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
+ u32 insn);
u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 94b62c1..1f44cf8 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -417,6 +417,35 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
return insn;
}
+u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
+ u32 insn)
+{
+ int shift;
+
+ switch (type) {
+ case AARCH64_INSN_REGTYPE_RT:
+ case AARCH64_INSN_REGTYPE_RD:
+ shift = 0;
+ break;
+ case AARCH64_INSN_REGTYPE_RN:
+ shift = 5;
+ break;
+ case AARCH64_INSN_REGTYPE_RT2:
+ case AARCH64_INSN_REGTYPE_RA:
+ shift = 10;
+ break;
+ case AARCH64_INSN_REGTYPE_RM:
+ shift = 16;
+ break;
+ default:
+ pr_err("%s: unknown register type encoding %d\n", __func__,
+ type);
+ return 0;
+ }
+
+ return (insn >> shift) & GENMASK(4, 0);
+}
+
static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
u32 insn,
enum aarch64_insn_register reg)
--
2.7.4
next prev parent reply other threads:[~2017-01-04 18:46 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-04 17:48 [PATCH v3 0/9] arm64: Expose CPUID registers via emulation Suzuki K Poulose
2017-01-04 17:48 ` [PATCH v3 1/9] arm64: cpufeature: treat unknown fields as RES0 Suzuki K Poulose
2017-01-05 17:08 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 2/9] arm64: cpufeature: remove explicit RAZ fields Suzuki K Poulose
2017-01-05 17:09 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 3/9] arm64: cpufeature: Cleanup feature bit tables Suzuki K Poulose
2017-01-05 17:18 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe value for features Suzuki K Poulose
2017-01-06 12:30 ` Catalin Marinas
2017-01-09 10:43 ` Suzuki K Poulose
2017-01-09 12:04 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 5/9] arm64: cpufeature: Define helpers for sys_reg id Suzuki K Poulose
2017-01-05 17:26 ` Catalin Marinas
2017-01-04 17:49 ` Suzuki K Poulose [this message]
2017-01-05 17:29 ` [PATCH v3 6/9] arm64: Add helper to decode register from instruction Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose
2017-01-05 18:06 ` Catalin Marinas
2017-01-06 11:18 ` Suzuki K Poulose
2017-01-04 17:49 ` [PATCH v3 8/9] arm64: cpufeature: Expose CPUID registers by emulation Suzuki K Poulose
2017-01-05 18:39 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 9/9] arm64: Documentation - Expose CPU feature registers Suzuki K Poulose
2017-01-06 12:16 ` Catalin Marinas
2017-01-09 10:59 ` Suzuki K Poulose
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