From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751059AbdAPTLz (ORCPT ); Mon, 16 Jan 2017 14:11:55 -0500 Received: from mga14.intel.com ([192.55.52.115]:34517 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750850AbdAPTLx (ORCPT ); Mon, 16 Jan 2017 14:11:53 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,240,1477983600"; d="scan'208";a="31264968" Message-ID: <1484593637.2133.152.camel@linux.intel.com> Subject: Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts From: Andy Shevchenko To: Jan Kiszka , Mark Brown Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Mack , Haojian Zhuang , Robert Jarzmik , linux-kernel@vger.kernel.org, Mika Westerberg , Jarkko Nikula Date: Mon, 16 Jan 2017 21:07:17 +0200 In-Reply-To: <7b15a0910a3ad861fd32161c72559bafa7b71e29.1484592296.git.jan.kiszka@siemens.com> References: <7b15a0910a3ad861fd32161c72559bafa7b71e29.1484592296.git.jan.kiszka@siemens.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.3-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-01-16 at 19:44 +0100, Jan Kiszka wrote: > When using the a device with edge-triggered interrupts, such as MSIs, > the interrupt handler has to ensure that there is a point in time > during > its execution where all interrupts sources are silent so that a new > event can trigger a new interrupt again. > > This is achieved here by looping over SSSR evaluation. We need to take > into account that SSCR1 may be changed by the transfer handler, thus > we > need to redo the mask calculation, at least regarding the volatile > interrupt enable bit (TIE). > So, more comments/questions below. >   >   sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); >   > - /* Ignore possible writes if we don't need to write */ > - if (!(sccr1_reg & SSCR1_TIE)) > - mask &= ~SSSR_TFS; > - >   /* Ignore RX timeout interrupt if it is disabled */ >   if (!(sccr1_reg & SSCR1_TINTE)) >   mask &= ~SSSR_TINT; >   > - if (!(status & mask)) > - return IRQ_NONE; > + while (1) { Can we switch to do-while and move previous block here? Btw, can TINTE bit be set again during a loop? > + /* Ignore possible writes if we don't need to write > */ > + if (!(sccr1_reg & SSCR1_TIE)) > + mask &= ~SSSR_TFS; >   > - if (!drv_data->master->cur_msg) { > - handle_bad_msg(drv_data); > - /* Never fail */ > - return IRQ_HANDLED; > - } > + if (!(status & mask)) > + return ret; > + > + if (!drv_data->master->cur_msg) { > + handle_bad_msg(drv_data); > + /* Never fail */ > + return IRQ_HANDLED; > + } > + > + ret |= drv_data->transfer_handler(drv_data); So, we might call handler several times. This needs to be commented in the code why you do so. >   > - return drv_data->transfer_handler(drv_data); > + status = pxa2xx_spi_read(drv_data, SSSR); Would it be possible to get all 1:s from the register (something/autosuspend just powered off it by timeout?) ? > + sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); > + } >  } >   >  /* -- Andy Shevchenko Intel Finland Oy