From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753912AbdASWmH (ORCPT ); Thu, 19 Jan 2017 17:42:07 -0500 Received: from ec2-52-27-115-49.us-west-2.compute.amazonaws.com ([52.27.115.49]:48106 "EHLO osg.samsung.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752446AbdASWmF (ORCPT ); Thu, 19 Jan 2017 17:42:05 -0500 From: Javier Martinez Canillas To: linux-kernel@vger.kernel.org Cc: Inki Dae , Andi Shyti , Shuah Khan , Marek Szyprowski , Andrzej Hajda , Javier Martinez Canillas , devicetree@vger.kernel.org, Kukjin Kim , Russell King , linux-samsung-soc@vger.kernel.org, Rob Herring , Mark Rutland , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] ARM: dts: exynos: Use correct mfc_pd async-bridge clock for Exynos5420 Date: Thu, 19 Jan 2017 19:29:55 -0300 Message-Id: <1484864995-10679-2-git-send-email-javier@osg.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484864995-10679-1-git-send-email-javier@osg.samsung.com> References: <1484864995-10679-1-git-send-email-javier@osg.samsung.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC power domain for Exynos5420") fixed an imprecise external abort error when the MFC registers were tried to be accessed and the needed clock for the asynchronous bridges were gated. But according to the Exynos5420 manual the "Gating AXI clock for MFC" is not CLK_ACLK333 but CLK_MFC. The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC but the correct clock should be used instead. Signed-off-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 906a1a42a7ea..ffb148ea91d6 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -294,7 +294,7 @@ reg = <0x10044060 0x20>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, - <&clock CLK_ACLK333>; + <&clock CLK_MFC>; clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; }; -- 2.7.4