From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935028AbdBQT71 (ORCPT ); Fri, 17 Feb 2017 14:59:27 -0500 Received: from mga01.intel.com ([192.55.52.88]:27177 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934948AbdBQT6d (ORCPT ); Fri, 17 Feb 2017 14:58:33 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,173,1484035200"; d="scan'208";a="67174471" From: Vikas Shivappa To: vikas.shivappa@intel.com Cc: linux-kernel@vger.kernel.org, x86@kernel.org, hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, peterz@infradead.org, ravi.v.shankar@intel.com, tony.luck@intel.com, fenghua.yu@intel.com, andi.kleen@intel.com, vikas.shivappa@linux.intel.com Subject: [PATCH 4/8] x86/intel_rct/mba: Add MBA structures and initialize MBA Date: Fri, 17 Feb 2017 11:58:51 -0800 Message-Id: <1487361535-9727-5-git-send-email-vikas.shivappa@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487361535-9727-1-git-send-email-vikas.shivappa@linux.intel.com> References: <1487361535-9727-1-git-send-email-vikas.shivappa@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MBA feature details like minimum bandwidth supported, b/w granularity etc are obtained via executing CPUID with EAX=10H ,ECX=3. Setup and initialize the MBA specific extensions to data structures like global list of RDT resources, RDT resource structure and RDT domain structure. Signed-off-by: Vikas Shivappa --- arch/x86/include/asm/intel_rdt.h | 17 +++++++ arch/x86/kernel/cpu/intel_rdt.c | 95 ++++++++++++++++++++++++++++++++++------ 2 files changed, 99 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h index d2eee45..af65b2a 100644 --- a/arch/x86/include/asm/intel_rdt.h +++ b/arch/x86/include/asm/intel_rdt.h @@ -11,6 +11,9 @@ #define IA32_L3_QOS_CFG 0xc81 #define IA32_L3_CBM_BASE 0xc90 #define IA32_L2_CBM_BASE 0xd10 +#define IA32_MBA_THRTL_BASE 0xd50 +#define MAX_MBA_THRTL 100u +#define MBA_IS_LINEAR 0x4 #define L3_QOS_CDP_ENABLE 0x01ULL @@ -74,6 +77,14 @@ struct rftype { * @default_ctrl: Specifies default cache cbm or mem b/w percent. * @min_cbm_bits: Minimum number of consecutive bits to be set * in a cache bit mask + * @max_delay: Max throttle delay. Delay is the hardware + * understandable value for memory b/w. + * @min_bw: Minimum memory bandwidth in percentage + * user can request + * @bw_gran: Bandwidth granularity + * @delay_linear: True if Mem b/w delay is in linear scale + * @mb_map: Mapping of mem b/w delay to + * b/w throttle percentage * @domains: All domains for this resource * @num_domains: Number of domains active * @msr_base: Base MSR address for CBMs @@ -92,6 +103,11 @@ struct rdt_resource { int cbm_len; int min_cbm_bits; u32 default_ctrl; + u32 max_delay; + u32 min_bw; + u32 bw_gran; + u32 delay_linear; + u32 *mb_map; struct list_head domains; int num_domains; int msr_base; @@ -141,6 +157,7 @@ enum { RDT_RESOURCE_L3DATA, RDT_RESOURCE_L3CODE, RDT_RESOURCE_L2, + RDT_RESOURCE_MBA, /* Must be the last */ RDT_NUM_RESOURCES, diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c index b76a518..130ce98 100644 --- a/arch/x86/kernel/cpu/intel_rdt.c +++ b/arch/x86/kernel/cpu/intel_rdt.c @@ -76,6 +76,14 @@ struct rdt_resource rdt_resources_all[] = { .cbm_idx_multi = 1, .cbm_idx_offset = 0 }, + { + .name = "MB", + .domains = domain_init(RDT_RESOURCE_MBA), + .msr_base = IA32_MBA_THRTL_BASE, + .cache_level = 3, + .cbm_idx_multi = 1, + .cbm_idx_offset = 0 + }, }; static int cbm_idx(struct rdt_resource *r, int closid) @@ -130,6 +138,51 @@ static inline bool cache_alloc_hsw_probe(void) return false; } +/* + * rdt_get_mb_table() - get a mapping of b/w percentage values + * exposed to user interface and the h/w understandable delay values. + * + * The non-linear delay values have the granularity of power of two + * and also the h/w does not guarantee a curve for configured delay + * values vs. actual b/w throttled. + * Hence we need a mapping that is pre caliberated for user to express + * the b/w in terms of any sensible number. + */ +static inline int rdt_get_mb_table(struct rdt_resource *r) +{ + /* + * There are no Intel SKUs as of now to support non-linear delay. + */ + r->mb_map = NULL; + + return -ENODEV; +} + +static bool rdt_get_mem_config(struct rdt_resource *r) +{ + union cpuid_0x10_3_eax eax; + union cpuid_0x10_x_edx edx; + u32 ebx, ecx; + + cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); + r->num_closid = edx.split.cos_max + 1; + r->max_delay = eax.split.max_delay + 1; + r->default_ctrl = MAX_MBA_THRTL; + if (ecx & MBA_IS_LINEAR) { + r->delay_linear = true; + r->min_bw = MAX_MBA_THRTL - r->max_delay; + r->bw_gran = MAX_MBA_THRTL - r->max_delay; + } else { + if (rdt_get_mb_table(r)) + return false; + } + + r->capable = true; + r->enabled = true; + + return true; +} + static void rdt_get_cache_config(int idx, struct rdt_resource *r) { union cpuid_0x10_1_eax eax; @@ -184,9 +237,8 @@ static inline bool get_rdt_resources(void) ret = true; } - if (boot_cpu_has(X86_FEATURE_MBA)) { - ret = true; - } + if (boot_cpu_has(X86_FEATURE_MBA)) + ret = rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]); return ret; } @@ -262,6 +314,30 @@ static struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id, return NULL; } +static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) +{ + int i; + + d->ctrl_val = kmalloc_array(r->num_closid, + sizeof(*d->ctrl_val), GFP_KERNEL); + if (!d->ctrl_val) + return -ENOMEM; + + /* + * Initialize the Control MSRs to having no control. + * For Cache Allocation: Set all bits in cbm + * For Memory Allocation: Set b/w requested to 100 + */ + for (i = 0; i < r->num_closid; i++) { + int idx = cbm_idx(r, i); + + d->ctrl_val[i] = r->default_ctrl; + wrmsrl(r->msr_base + idx, d->ctrl_val[i]); + } + + return 0; +} + /* * domain_add_cpu - Add a cpu to a resource's domain list. * @@ -277,7 +353,7 @@ static struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id, */ static void domain_add_cpu(int cpu, struct rdt_resource *r) { - int i, id = get_cache_id(cpu, r->cache_level); + int id = get_cache_id(cpu, r->cache_level), ret; struct list_head *add_pos = NULL; struct rdt_domain *d; @@ -298,19 +374,12 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r) d->id = id; - d->ctrl_val = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL); - if (!d->ctrl_val) { + ret = domain_setup_ctrlval(r, d); + if (ret) { kfree(d); return; } - for (i = 0; i < r->num_closid; i++) { - int idx = cbm_idx(r, i); - - d->ctrl_val[i] = r->default_ctrl; - wrmsrl(r->msr_base + idx, d->ctrl_val[i]); - } - cpumask_set_cpu(cpu, &d->cpu_mask); list_add_tail(&d->list, add_pos); r->num_domains++; -- 1.9.1