From: Leo Yan <leo.yan@linaro.org>
To: Jonathan Corbet <corbet@lwn.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Wei Xu <xuwei5@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Guodong Xu <guodong.xu@linaro.org>,
John Stultz <john.stultz@linaro.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, mike.leach@linaro.org,
Suzuki.Poulose@arm.com, sudeep.holla@arm.com
Cc: Leo Yan <leo.yan@linaro.org>
Subject: [PATCH v5 1/9] coresight: bindings for CPU debug module
Date: Sun, 26 Mar 2017 02:23:09 +0800 [thread overview]
Message-ID: <1490466197-29163-2-git-send-email-leo.yan@linaro.org> (raw)
In-Reply-To: <1490466197-29163-1-git-send-email-leo.yan@linaro.org>
According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
Chapter 'Part H: External debug', the CPU can integrate debug module
and it can support self-hosted debug and external debug. Especially
for supporting self-hosted debug, this means the program can access
the debug module from mmio region; and usually the mmio region is
integrated with coresight.
So add document for binding debug component, includes binding to APB
clock; and also need specify the CPU node which the debug module is
dedicated to specific CPU.
Suggested-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
.../bindings/arm/coresight-cpu-debug.txt | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
new file mode 100644
index 0000000..7ef3824
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
@@ -0,0 +1,48 @@
+* CoreSight CPU Debug Component:
+
+CoreSight CPU debug component are compliant with the ARMv8 architecture
+reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+external debug module is mainly used for two modes: self-hosted debug and
+external debug, and it can be accessed from mmio region from Coresight
+and eventually the debug module connects with CPU for debugging. And the
+debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc;
+usually every CPU has one dedicated debug module to be connected.
+
+Required properties:
+
+- compatible : should be "arm,coresight-cpu-debug"; supplemented with
+ "arm,primecell" since this driver is using the AMBA bus
+ interface.
+
+- reg : physical base address and length of the register set.
+
+- clocks : the clock associated to this component.
+
+- clock-names : the name of the clock referenced by the code. Since we are
+ using the AMBA framework, the name of the clock providing
+ the interconnect should be "apb_pclk" and the clock is
+ mandatory. The interface between the debug logic and the
+ processor core is clocked by the internal CPU clock, so it
+ is enabled with CPU clock by default.
+
+- cpu : the CPU phandle the debug module is affined to. When omitted
+ the module is considered to belong to CPU0.
+
+Optional properties:
+
+- power-domains: a phandle to the debug power domain. We use "power-domains"
+ binding to turn on the debug logic if it has own dedicated
+ power domain and if necessary to use "idle_constraint" in
+ kernel command line or debugfs node to constrain idle states
+ to ensure registers in the CPU power domain are accessible.
+
+Example:
+
+ debug@f6590000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6590000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
--
2.7.4
next prev parent reply other threads:[~2017-03-25 18:25 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-25 18:23 [PATCH v5 0/9] coresight: enable debug module Leo Yan
2017-03-25 18:23 ` Leo Yan [this message]
2017-03-30 22:49 ` [PATCH v5 1/9] coresight: bindings for CPU " Rob Herring
2017-03-31 9:04 ` Suzuki K Poulose
2017-03-25 18:23 ` [PATCH v5 2/9] doc: Add documentation for Coresight CPU debug Leo Yan
2017-03-25 18:23 ` [PATCH v5 3/9] coresight: of_get_coresight_platform_data: Add missing of_node_put Leo Yan
2017-03-25 18:23 ` [PATCH v5 4/9] coresight: refactor with function of_coresight_get_cpu Leo Yan
2017-03-31 9:05 ` Suzuki K Poulose
2017-03-25 18:23 ` [PATCH v5 5/9] coresight: use const for device_node structures Leo Yan
2017-04-04 21:48 ` Stephen Boyd
2017-03-25 18:23 ` [PATCH v5 6/9] coresight: add support for CPU debug module Leo Yan
2017-03-27 16:34 ` Suzuki K Poulose
2017-03-29 3:07 ` Leo Yan
2017-03-29 9:07 ` Suzuki K Poulose
2017-03-29 10:27 ` Leo Yan
2017-03-29 10:31 ` Suzuki K Poulose
2017-03-29 10:37 ` Leo Yan
2017-03-29 15:50 ` Suzuki K Poulose
2017-03-29 15:17 ` Mike Leach
2017-03-30 1:18 ` Leo Yan
2017-03-29 15:41 ` Mathieu Poirier
2017-03-28 16:50 ` Mathieu Poirier
2017-03-29 1:54 ` Leo Yan
2017-03-29 14:56 ` Mike Leach
2017-03-30 1:03 ` Leo Yan
2017-03-30 9:00 ` Suzuki K Poulose
2017-03-30 13:51 ` Leo Yan
2017-03-30 15:47 ` Sudeep Holla
2017-03-29 16:55 ` Mathieu Poirier
2017-03-30 1:59 ` Leo Yan
2017-03-30 15:46 ` Mathieu Poirier
2017-03-30 16:04 ` Sudeep Holla
2017-03-30 15:56 ` Sudeep Holla
2017-03-31 0:54 ` Leo Yan
2017-03-25 18:23 ` [PATCH v5 7/9] clk: hi6220: add debug APB clock Leo Yan
2017-04-04 21:51 ` Stephen Boyd
2017-04-06 13:59 ` Leo Yan
2017-03-25 18:23 ` [PATCH v5 8/9] arm64: dts: hi6220: register debug module Leo Yan
2017-03-25 18:23 ` [PATCH v5 9/9] arm64: dts: qcom: msm8916: Add debug unit Leo Yan
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