From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753272AbdC0Xr0 (ORCPT ); Mon, 27 Mar 2017 19:47:26 -0400 Received: from mga07.intel.com ([134.134.136.100]:42526 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752780AbdC0XrR (ORCPT ); Mon, 27 Mar 2017 19:47:17 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,234,1486454400"; d="scan'208";a="1112748969" Message-ID: <1490658399.2647.14.camel@ranerica-desktop> Subject: Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention From: Ricardo Neri To: Stas Sergeev Cc: Andy Lutomirski , Ingo Molnar , Thomas Gleixner , "H. Peter Anvin" , Andy Lutomirski , Borislav Petkov , Peter Zijlstra , Andrew Morton , Brian Gerst , Chris Metcalf , Dave Hansen , Paolo Bonzini , Liang Z Li , Masami Hiramatsu , Huang Rui , Jiri Slaby , Jonathan Corbet , "Michael S. Tsirkin" , Paul Gortmaker , Vlastimil Babka , Chen Yucong , Alexandre Julliard , Fenghua Yu , "Ravi V. Shankar" , Shuah Khan , "linux-kernel@vger.kernel.org" , X86 ML , linux-msdos@vger.kernel.org, wine-devel@winehq.org Date: Mon, 27 Mar 2017 16:46:39 -0700 In-Reply-To: <6331deea-e9b0-fcfe-b75d-8100f37a615a@list.ru> References: <20170308003254.27833-1-ricardo.neri-calderon@linux.intel.com> <79ba0fff-4c01-2bfa-06cb-5cfc98dd710c@list.ru> <997ba581-ecfa-b773-a48e-85b92a439836@list.ru> <1489022122.131264.33.camel@ranerica-desktop> <63231222-5b42-c8c9-02f0-0afbe702d8b5@list.ru> <1489190396.131264.47.camel@ranerica-desktop> <6331deea-e9b0-fcfe-b75d-8100f37a615a@list.ru> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2017-03-14 at 00:25 +0300, Stas Sergeev wrote: > 11.03.2017 02:59, Ricardo Neri пишет: > > On Fri, 2017-03-10 at 14:33 +0300, Stas Sergeev wrote: > > > >> Why would you need one? > >> Or do you really want to allow these instructions > >> in v86 by the means of emulation? If so - this wasn't > >> clearly stated in the patch description, neither it was > >> properly discussed, it seems. > > It str and sldt can be emulated in vm86 but as Andy mention, the > > behavior sould be the same with and without emulation. > Why would you do that? > I looked up the dosemu2 CPU simulator code that > is used under x86-64. It says this: Stas, I apologize for the delayed reply; I missed your e-mail. > --- > CODE_FLUSH(); > if (REALMODE()) goto illegal_op; > PC += ModRMSim(PC+1, mode) + 1; > error("SLDT not implemented\n"); > break; > case 1: /* STR */ > /* Store Task Register */ > CODE_FLUSH(); > if (REALMODE()) goto illegal_op; > PC += ModRMSim(PC+1, mode) + 1; > error("STR not implemented\n"); > break; > ... > case 0: /* SGDT */ > /* Store Global Descriptor Table > Register */ > PC++; PC += ModRM(opc, PC, > mode|DATA16|MSTORE); > error("SGDT not implemented\n"); > break; > case 1: /* SIDT */ > /* Store Interrupt Descriptor Table > Register */ > PC++; PC += ModRM(opc, PC, > mode|DATA16|MSTORE); > error("SIDT not implemented\n"); > break; > --- > > It only implements smsw. > So maybe you can make your code much > simpler and remove the unneeded emulation? > Same is for prot mode. Do you mean the unneeded emulation for SLDT and STR? > You know the wine's > requirements now - they are very small. And > dosemu doesn't need anything at all but smsw. > And even smsw is very rare. But emulation is still needed for SMSW, right? The majority of my patches deal with computing the effective based on the instruction operands and linear addresses based on the effective address and the segment descriptor. Only two or three patches deal with identifying particular UMIP-protected instructions. Not having to worry about STR and SLDT in vm86 could simplify things a bit, though. Thanks and BR, Ricardo