From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756076AbdC2LVi (ORCPT ); Wed, 29 Mar 2017 07:21:38 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:52936 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932213AbdC2LUv (ORCPT ); Wed, 29 Mar 2017 07:20:51 -0400 From: Vlad Zakharov To: "sboyd@codeaurora.org" , "mturquette@baylibre.com" , "Vladislav.Zakharov@synopsys.com" CC: "robh@kernel.org" , "linux-kernel@vger.kernel.org" , "Jose.Abreu@synopsys.com" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-snps-arc@lists.infradead.org" Subject: Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver Thread-Topic: [PATCH v2] clk/axs10x: introduce AXS10X pll driver Thread-Index: AQHSjEP84oiIqPaSbUyCNi/neN7GXaGDGAWAgACwd4CAJ/p6AA== Date: Wed, 29 Mar 2017 11:20:46 +0000 Message-ID: <1490786446.32756.4.camel@synopsys.com> References: <1487682670-4164-1-git-send-email-vzakhar@synopsys.com> <1488547113.2557.44.camel@synopsys.com> <20170303235005.GV25384@codeaurora.org> In-Reply-To: <20170303235005.GV25384@codeaurora.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.121.8.100] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v2TBN141001644 Hi Stephen, Michael, On Fri, 2017-03-03 at 15:50 -0800, Stephen Boyd wrote: > On 03/03, Vlad Zakharov wrote: > > > > Hi Michael, Stephen, > > > > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote: > > > > > > AXS10X boards manages it's clocks using various PLLs. These PLL has same > > > dividers and corresponding control registers mapped to different addresses. > > > So we add one common driver for such PLLs. > > > > > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and > > > ODIV. Output clock value is managed using these dividers. > > > > > > We add pre-defined tables with supported rate values and appropriate > > > configurations of IDIV, FBDIV and ODIV for each value. > > > > > > As of today we add support for PLLs that generate clock for the > > > following devices: > > >  * ARC core on AXC CPU tiles. > > >  * ARC PGU on ARC SDP Mainboard. > > > and more to come later. > > > > > > Acked-by: Rob Herring > > > Signed-off-by: Vlad Zakharov > > > Signed-off-by: Jose Abreu > > > Cc: Michael Turquette > > > Cc: Stephen Boyd > > > Cc: Mark Rutland > > > > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it. > > > > I haven't reviewed it yet. The merge window is upon us right now > so I'll probably get to going through the queue this weekend/next > week. > Please treat this message as a polite reminder to review my patch. It is required for some subsystems on our boards, e.g. for ARC PGU. Thanks. -- Best regards, Vlad Zakharov