From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753790AbdDDNoE (ORCPT ); Tue, 4 Apr 2017 09:44:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6763 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753272AbdDDNoD (ORCPT ); Tue, 4 Apr 2017 09:44:03 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Apr 2017 06:43:57 -0700 From: Mikko Perttunen To: , , , CC: , , , Mikko Perttunen Subject: [PATCH v2 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 Date: Tue, 4 Apr 2017 16:43:37 +0300 Message-ID: <1491313417-25085-3-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1491313417-25085-1-git-send-email-mperttunen@nvidia.com> References: <1491313417-25085-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen --- v2: - Only one regs entry arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 3ea5e6369bc3..c023af0be43d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -347,6 +347,13 @@ reg-names = "pmc", "wake", "aotag", "scratch"; }; + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x3fffff>; + + nvidia,bpmp = <&bpmp>; + }; + sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; -- 2.1.4