[PATCH] x86/intel_rdt: Fix two typos in Documentation

[Xiaochen Shen <xiaochen.shen@intel.com>]

Both typos are in example 3.

Because cache id 0 is the only cache id, the ";" is redundant in
"# echo "L3:0=ffc00;" > p0/schemata".

And "C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
6-7 instead of wanted core 4-7.

Correct the typos to avoid confusion.

Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 Documentation/x86/intel_rdt_ui.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt
index 51cf6fa..cd752c1 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -206,12 +206,12 @@ Next we make a resource group for our real time cores and give
 it access to the "top" 50% of the cache on socket 0.
 
 # mkdir p0
-# echo "L3:0=ffc00;" > p0/schemata
+# echo "L3:0=ffc00" > p0/schemata
 
 Finally we move core 4-7 over to the new group and make sure that the
 kernel and the tasks running there get 50% of the cache.
 
-# echo C0 > p0/cpus
+# echo F0 > p0/cpus
 
 4) Locking between applications
 
-- 
1.8.3.1