From: Laxman Dewangan <ldewangan@nvidia.com>
To: <thierry.reding@gmail.com>, <robh+dt@kernel.org>, <jonathanh@nvidia.com>
Cc: <mark.rutland@arm.com>, <linux-pwm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Laxman Dewangan <ldewangan@nvidia.com>
Subject: [PATCH V3 2/4] pwm: tegra: Increase precision in pwm rate calculation
Date: Fri, 7 Apr 2017 15:04:00 +0530 [thread overview]
Message-ID: <1491557642-15940-3-git-send-email-ldewangan@nvidia.com> (raw)
In-Reply-To: <1491557642-15940-1-git-send-email-ldewangan@nvidia.com>
The rate of the PWM calculated as follows:
hz = NSEC_PER_SEC / period_ns;
rate = (rate + (hz / 2)) / hz;
This has the precision loss in lower PWM rate.
Change this to have more precision as:
hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns);
rate = DIV_ROUND_CLOSEST(rate * 100, hz)
Example:
1. period_ns = 16672000, PWM clock rate is 200KHz.
Based on old formula
hz = NSEC_PER_SEC / period_ns
= 1000000000ul/16672000
= 59 (59.98)
rate = (200K + 59/2)/59 = 3390
Based on new method:
hz = 5998
rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
If we measure the PWM signal rate, we will get more accurate period
with rate value of 3334 instead of 3390.
2. period_ns = 16803898, PWM clock rate is 200KHz.
Based on old formula:
hz = 59, rate = 3390
Based on new formula:
hz = 5951, rate = 3360
The PWM signal rate of 3360 is more near to requested period than 3333.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from v1:
- None
Changes from V2:
- Fix the commit message with exact formula used.
---
drivers/pwm/pwm-tegra.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 0a688da..21518be 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -76,6 +76,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
unsigned long long c = duty_ns;
unsigned long rate, hz;
+ unsigned long long ns100 = NSEC_PER_SEC;
u32 val = 0;
int err;
@@ -94,9 +95,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* cycles at the PWM clock rate will take period_ns nanoseconds.
*/
rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
- hz = NSEC_PER_SEC / period_ns;
- rate = (rate + (hz / 2)) / hz;
+ /* Consider precision in PWM_SCALE_WIDTH rate calculation */
+ ns100 *= 100;
+ hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
+ rate = DIV_ROUND_CLOSEST(rate * 100, hz);
/*
* Since the actual PWM divider is the register's frequency divider
--
2.1.4
next prev parent reply other threads:[~2017-04-07 9:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-07 9:33 [PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Laxman Dewangan
2017-04-07 9:33 ` [PATCH V3 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation Laxman Dewangan
2017-04-07 9:34 ` Laxman Dewangan [this message]
2017-04-12 17:19 ` [PATCH V3 2/4] pwm: tegra: Increase precision in pwm rate calculation Thierry Reding
2017-04-07 9:34 ` [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Laxman Dewangan
2017-04-07 10:25 ` Jon Hunter
2017-04-10 20:13 ` Rob Herring
2017-04-07 9:34 ` [PATCH V3 4/4] pwm: tegra: Add support to configure pin state " Laxman Dewangan
2017-04-07 10:27 ` Jon Hunter
2017-04-12 17:18 ` [PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Thierry Reding
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