From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1953744AbdDYTQr (ORCPT ); Tue, 25 Apr 2017 15:16:47 -0400 Received: from mail-bn3nam01on0075.outbound.protection.outlook.com ([104.47.33.75]:50880 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1947509AbdDYTQ1 (ORCPT ); Tue, 25 Apr 2017 15:16:27 -0400 Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=amd.com; From: Yazen Ghannam To: CC: Yazen Ghannam , Tony Luck , Borislav Petkov , , Subject: [PATCH v3 2/2] x86/mce/AMD: Carve out SMCA bank configuration Date: Tue, 25 Apr 2017 14:16:12 -0500 Message-ID: <1493147772-2721-2-git-send-email-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493147772-2721-1-git-send-email-Yazen.Ghannam@amd.com> References: <1493147772-2721-1-git-send-email-Yazen.Ghannam@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: MWHPR21CA0068.namprd21.prod.outlook.com (10.172.93.158) To BN6PR1201MB0131.namprd12.prod.outlook.com (10.174.114.144) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d414d330-38cf-4b48-8157-08d48c0f9035 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(48565401081)(201703131423075)(201703031133081);SRVR:BN6PR1201MB0131; X-Microsoft-Exchange-Diagnostics: 1;BN6PR1201MB0131;3:HQ/LzezAe9WA9Hk4kMT/o0u8JPSOHWklgnJli0cd2r3fFseky9ewYypmgEx5JD65knnAijWRqaV2mgnAeBm9xXuBCn6xfZhYjYuFpOz8aNvmONV40OiljqhG2tDbUVby/nhbPpgWb/Vb1myOhsjuwHlWkJeyGi1keDp259/TNq9xOqiaDTBBfJjYj4mOkGDhNd0sNiEmn0zqDBWdfyJ+laSp5krGhlbfc94V6YX+w6D9k1XIkupr6Xf4vNPDn86snT7gqHYEsRC6f0OUaP7A6KccLLkWaeC6to3x4bAQ//3kr0kzFkWAjeiU7Py89rC5gaTtoDQ6P9IyvnI9jW1QlMWAqdqmVIS6Ighqd8moA94=;25:Vc5mGPEvUKAfIv3bbiY/jSIIRN7e2ZOs9RafExwJ5N79zvXuTKK3dIT2rFtWT4bhyQxyKzcPXqWAhnjsWSLq2ohW4UO/7bM3M+/BqfyzCCpfzv/m/hhcDidpJENErQA9pXVZKVygr+pkmtxOcC1DPnmZS5GlGLajlf4rQROUpb/v669ZVccWjfhu5+B4Lv+p91er5GErXHLO2g5GPB0GcHmCIfl0qGEt3FgHfdSfOWktRuuTzmmH2pR2crdn/dpecOQr2C8vEf3TvLxnLpG+FCzXDQGEFv0tlyOUQ4DBu1iu4RbajBsIuGx81ZXejKjkAsTq5FUfBGmufAEi9paBIPIreGCc/XvMxzUPRVf+evqWkl9nj0v50oSQMn+hE1b9LVy0bT/vD9/D7hvzk9LB8gRHvCTuJK7QIdekeZ/uxjwvX5LzF4k5EQrFVbBUi/VbU8RbDsqO92sPCZeDs4ApiA== X-Microsoft-Exchange-Diagnostics: 1;BN6PR1201MB0131;31:z8+UXKebgL/7XSihNZiz9DmBtwpiYKrQa6zznKUoSwC32SdW14eiwJjcIPGC67v9dex6zKYbrrID2gensM7gvgwg6lvMioL1SvcW71nIEK2S+qRKnDdnkaOYJYa2ivIlSek4LXkxD17XFvZTr00Rqq+y40BZnmYiLXlgrNs1iRhUlkd76YNnqJry3Cojqblfq0X6zJdo/Uxbbr8aNRPY3eD9lMqndQtIqZv2t1gIAQ8=;20:FP+FdOY1QRnbLSIJekkTi9aQzijQGf3/TpWcVYVcMKAdG7xpMB5QymBeCaZmnJImyjO/LPUv3QdOySGf7zb8gpoEIHYnkGNZf6Z7CzGH5bjj6JBWNDeYY8VUJVIetraA+Bf7hjW1BPlCB0Mt7nXuTiI+aP6fM0czDTah/x2wo5SYBR/wLLY5xj2FAxdDi8aWb5/GM2YEgoM6Q60di4CZX63YLEpbCjXgfMf6/s0QV2955/ijRxTvKVj8O16es03zGuHDH5AvNbEqkc9TkNXu3D8BWNDJF+oAcESDV1sisa+xlfjXCVH4LvDng4+GR7wPH6trNeLQAA/4cseocEB7xXTAVZcClOm+eNCA76dU+W+diCmqyEUW++q6WbBwXycjht1YFANKWiuhrYuKCVdjcdz8+4AnweLKSboXGMcf7PZsJ1f2oxBZdcemLUoZlf+y12pSxylRlZYnFyWiX9rLmtCWhNtqRYJq5Es8RvpqblwxC+u11OV/N5fyErQBfev7 X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110)(42068640409301); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(93006095)(93001095)(3002001)(10201501046)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(20161123562025)(20161123560025)(20161123555025)(20161123564025)(6072148);SRVR:BN6PR1201MB0131;BCL:0;PCL:0;RULEID:;SRVR:BN6PR1201MB0131; X-Microsoft-Exchange-Diagnostics: 1;BN6PR1201MB0131;4:cqp+D/uZVUYs1L6pHXb6z20fz8RaqE87ZgMmUbv3fxZd9Qyx5w2mN+l+wUxJMtBmm8v88W1ilfR7FfbjH9LjuKOMr/st34bo1F4pqIBt09+Il6GJg6UP8GIVXsVNxpb+xw9Mhsnbh3TyQfaWfZnXQCAtY8jcov/d6KvNDdqMr1DvE9gde/RLhTTe1tadkPgcNxWsuSsYB7hVpDXLmikh0YF58YJ8Y+P7bL6mAvbdYJpE9wiPcQFTQLZFjOssi+K6T81zfOvgOfUC35DFh1sqEIej4r0YluK4U1biIKCVSCl9ci0OZYiQsp3KcnVn3XrmDboSRSWAGAmXKA7H459VpGBIYzs8GqEd8LuNd9nZ0v2nRcccErP4jfw4zENst1s2nVLRmtpzJ3AjkQW8Ib3Ql5PPev+Mj74s2rAp9V2ovgwiCTJYmmQJZaAht1FmdceTX9huAMRlOu/UN4JTXVA9Cgq/seFtXhDVPjPp2VmSUfPqOYXYPzLr5wI+3wK4n/RLIZcmUzv0twKk3O2xWFOw2gyD5U8q71ng1UxChBtSiejKowU2E/sAU3hj/3GC0nlB73xA/t3LkX6UUBLK/+0GQFmGqoD97qFwjr2UHdn3dVliztnw8a5qxLrAfPmT/DZ6Ww3wGz1g1fXYNSHhv2hVQm+CQgPR0kmviMxzvN1/xGihImGcZ/Y/SzQbl9isr026f2yLt7+0VPmJ2NCG6AThGMoR0+A9Vaoff5IyfoJG29cPgYpsDKO3WEp6AlJvNsXNz7qdw3q48tKfqYsQxLqXWtz6en/PfFuixJWibRY+Yoq8egUcb0PQ/GSqkQfZ6vE9 X-Forefront-PRVS: 0288CD37D9 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4630300001)(6009001)(39450400003)(39860400002)(39840400002)(39400400002)(39410400002)(39850400002)(305945005)(6116002)(6916009)(7736002)(53416004)(6666003)(42186005)(2950100002)(3846002)(53936002)(6306002)(15650500001)(2351001)(189998001)(54906002)(5003940100001)(38730400002)(47776003)(76176999)(66066001)(50986999)(110136004)(2906002)(5660300001)(8676002)(48376002)(25786009)(6486002)(50466002)(81166006)(36756003)(50226002)(4326008)(86362001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN6PR1201MB0131;H:yaz-diesel.amd.com;FPR:;SPF:None;MLV:sfv;LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;BN6PR1201MB0131;23:G4PuXP430qmM5F0XEKY39/JPKSYC6ugcGXaKNSQ?= =?us-ascii?Q?WzLKplzWNyByXMago4pstUc6leCj4EFlEoVOkvSnmqCJflfw9zirBvl5V4VR?= =?us-ascii?Q?BUTLxoMke7qlMB/oH2BzgyEwC0TlB93aKYz+328DaNgwtBk+vZIjHi1Nz5x4?= =?us-ascii?Q?0nW5IsBile6bQ0gY8t9G/Zgj4xW2iXJ6psbgXfrcMk3VDyciKW6odeymZKtp?= =?us-ascii?Q?oNC4c2t9fM1lhP01jyn2CJggm2nWbamWKntHcn/ll0scNYU4VR3WvcUIgeD8?= =?us-ascii?Q?Crgmaf38FGTHlxv8XAgrPoFCzSTzTntP5Eo8h+CofMLXiFfgdxBvH1Hc83nB?= =?us-ascii?Q?Yhd5SNPCKmTc5d48obFEvJA+ZjHN2CKZevjHASUas7ieXg4Zda5uPbBsex99?= =?us-ascii?Q?lxRcQCD3IJgF7nk5JNmwHHboD6l0LpHbshcX5IiFH4Wk8HzrB6SWaTrxkhhc?= =?us-ascii?Q?byaF5rhs3arIuJ4zQvlC9x2YJc+v3nxzpo67uYzcDIkmM3uUAK+1a6b2xV82?= =?us-ascii?Q?UfNufwinG6IEzrXqjMlv2GSmjCSgoHn9kSlet/SmhUIxFJOQSjuJ0nRN4P7P?= =?us-ascii?Q?weZluNcZSQmhXst+AlBzYY9MQcokvGRLQYXHzJTSvjFWqprLJzahFaYKeWSz?= =?us-ascii?Q?OpeNb1NA4sD3kcBR8PujDtYJ3hIkTD1MDA1HKbQ1n0AC1yMd+KR/rOZCmyay?= =?us-ascii?Q?NhgA8yHXMuP2Z31q6fYfERQoVcdL6JNiCZFwXgTmO/yRuXgM65+BHV6pdoUw?= =?us-ascii?Q?FA1PXChRV3I/s0+JaFoGDg7LElGwyk7BErdLdZh0uKTVgGQy12YF3F2svrbq?= =?us-ascii?Q?dO3hdzYpZJvdoMcJfwOuSSDZH8MsfrsDju0ms7AE3NKxrO129T7g0rBFQNml?= =?us-ascii?Q?E7gVsOVv5bFkh1hRtanKFCZWpwzV8lCn5zqths4HWEdPbCVMMfZClZa/3E1m?= =?us-ascii?Q?ep+daHYKb5nQW2Ur1sFUfdAu4AM/WWA2T6xKUDM38aoy8GtNJoXJL27asw/v?= =?us-ascii?Q?kH7mpusSc8vPbwfoPhOXHfgdde12q1DF3S4mbF83folC7xncwZsdZCaWM7yn?= =?us-ascii?Q?U6NwrlzAWP4Pob4NIEx6p8KcV3CY6?= X-Microsoft-Exchange-Diagnostics: 1;BN6PR1201MB0131;6:NLNxCeKSMw/2fSpa3xdr57LY3RBcHhjTwhj0Om4ricZOUmOn6Xx/qhV1g9sBTti4RD06uGnVEOgGnU7+DGJSVKidKIuOlIkuRzGaKgwdnM+XZ211qLxatJqIw6BWcnqPFV++OU3t0qv03hO/p9QrlUU+/mKnQiGHi8LBWnKzzuA9ERKiyelOtom4CYu1cMacCR7Sczy83aRIPwiK1LhDdEX4tDpA9XBgF+G6XC+b6zn0AED+jjfdO8/oQYdq5Fx8qxgi4mleANlAY/Hzt3bsVTr+p9moJ9ugcSvgR6VIfVXB/P8j9puALO40We4CUJhlQsQMQI5OnaWjc/uzCabgZzM04ZV4F5JDERETCehmKWMXd4OIuxo0iPJtGEHQPzMFsL6Fnj0ns/js84tuswdFs0WRHeMOt/PieE4IItIqOm4TcyDcPRjl1REReYWGIWRBptgWQYA1rVsc0+69UKyZBQ3hNcgVEyhsuHof+UFGgXzSQ9fTVOiAE0ARWx2HGb60DUHC6cPOSRoJHm1jJ8iJXexa9nSdt9PPv1s6E8Alb8Q=;5:U2UjNwFahPcqxzi1IUqX8XQwHYvK2QxdMTmPlPL3gvE9AnX5V4q9oe/4J4kM7wnxXemo1PC1UjJnWGHHGUX7Fhs3pW95JvGv7E3y8M5keA/H4yjyVP7nYr+eX7HQdaL8ipvSLufg4K6Y/8rLMLNvjA==;24:Oboy+GraNieyojZco5yG0ScU3zP3I0hyh4sfsiOaj9b9oj/cD5h8gqrkxh1hHj/U98zSQuUEEmmgg2ghXaUT9ALfEtmQSur1BFFcAximiHY= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1;BN6PR1201MB0131;7:MdVU7lrYyuR9wRdZ95hVocm3R81RyAmEoFm2fTnMgkv3lrmlyB7266JKuJZDHyqqK9e1pPMkaKxv7VDLOCUxelarwDF9yNCvBLZheEcJlNIv6QaH+V/BY/WejDKfYoW2A+NtyUGzwoveZ4NJ+R+SRNIsxh9N97KC3z1N37wpNCU71oV0gg/hUfMPFutpKKpgHdD865Z+b0ikK/WeeGrzDFhfMESHYq38A/S+SdI0HDoCO0r3wsXg1R9ysWs4TgGILNx6AeR1SmkuqyaRByn5eAPEWWeJctT5b/F20PQf0Kknt7c5MDxk0QiZkKWviRN8z5gp0I5p6da/xOLQtvudBA==;20:adVFL8tZcblMyleksTJwq+mQRiuTrA80TxT6ExHZHFXUgyLKose8DbMgLAgPGUO3bQetTi2qvS8+0mrbx98EuPlgNNNWzyoYbhOzUwU/Kg+rgJH+4+ZSs8EaWRl+QJL619whaXGUELzzSfLwJcST1sfrsgKDdCLzIig1d6+JkvEJahbBM0UlyqhFhRjNId0n4qT8lVtyUShYdt3wD4CBSyTnBKOSUZte9xWN5/w30lffrTKBFY2UuchiaaHHRFj0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2017 19:16:22.4935 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0131 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Scalable MCA systems have a new MCA_CONFIG register that we use to configure each bank. We currently use this when we set up thresholding. However, this is logically separate. Group all SMCA-related initialization into a single, separate function. This includes setting MCA_CONFIG and gathering SMCA bank info. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/1491326672-48298-2-git-send-email-Yazen.Ghannam@amd.com v2->v3: - Pass in CPU to smca_configure(). v1->v2: - Merge get_smca_bank_info() and set_smca_config() into smca_configure(). arch/x86/kernel/cpu/mcheck/mce_amd.c | 76 ++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index e6e507d..f97bc60 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -164,17 +164,48 @@ static void default_deferred_error_interrupt(void) } void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; -static void get_smca_bank_info(unsigned int bank) +static void smca_configure(unsigned int bank, unsigned int cpu) { - unsigned int i, hwid_mcatype, cpu = smp_processor_id(); + unsigned int i, hwid_mcatype; struct smca_hwid *s_hwid; - u32 high, instance_id; + u32 high, low; + u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); + + /* Set appropriate bits in MCA_CONFIG */ + if (!rdmsr_safe(smca_config, &low, &high)) { + /* + * OS is required to set the MCAX bit to acknowledge that it is + * now using the new MSR ranges and new registers under each + * bank. It also means that the OS will configure deferred + * errors in the new MCx_CONFIG register. If the bit is not set, + * uncorrectable errors will cause a system panic. + * + * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) + */ + high |= BIT(0); + + /* + * SMCA sets the Deferred Error Interrupt type per bank. + * + * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us + * if the DeferredIntType bit field is available. + * + * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the + * high portion of the MSR). OS should set this to 0x1 to enable + * APIC based interrupt. First, check that no interrupt has been + * set. + */ + if ((low & BIT(5)) && !((high >> 5) & 0x3)) + high |= BIT(5); + + wrmsr(smca_config, low, high); + } /* Collect bank_info using CPU 0 for now. */ if (cpu) return; - if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instance_id, &high)) { + if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { pr_warn("Failed to read MCA_IPID for bank %d\n", bank); return; } @@ -191,7 +222,7 @@ static void get_smca_bank_info(unsigned int bank) smca_get_name(s_hwid->bank_type)); smca_banks[bank].hwid = s_hwid; - smca_banks[bank].id = instance_id; + smca_banks[bank].id = low; smca_banks[bank].sysfs_id = s_hwid->count++; break; } @@ -433,7 +464,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, int offset, u32 misc_high) { unsigned int cpu = smp_processor_id(); - u32 smca_low, smca_high, smca_addr; + u32 smca_low, smca_high; struct threshold_block b; int new; @@ -457,37 +488,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, goto set_offset; } - smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); - - if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { - /* - * OS is required to set the MCAX bit to acknowledge that it is - * now using the new MSR ranges and new registers under each - * bank. It also means that the OS will configure deferred - * errors in the new MCx_CONFIG register. If the bit is not set, - * uncorrectable errors will cause a system panic. - * - * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) - */ - smca_high |= BIT(0); - - /* - * SMCA sets the Deferred Error Interrupt type per bank. - * - * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us - * if the DeferredIntType bit field is available. - * - * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the - * high portion of the MSR). OS should set this to 0x1 to enable - * APIC based interrupt. First, check that no interrupt has been - * set. - */ - if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) - smca_high |= BIT(5); - - wrmsr(smca_addr, smca_low, smca_high); - } - /* Gather LVT offset for thresholding: */ if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) goto out; @@ -516,7 +516,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) for (bank = 0; bank < mca_cfg.banks; ++bank) { if (mce_flags.smca) - get_smca_bank_info(bank); + smca_configure(bank, cpu); for (block = 0; block < NR_BLOCKS; ++block) { address = get_block_address(cpu, address, low, high, bank, block); -- 2.7.4