From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1956681AbdDZJd1 (ORCPT ); Wed, 26 Apr 2017 05:33:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:15471 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2993831AbdDZJ0a (ORCPT ); Wed, 26 Apr 2017 05:26:30 -0400 From: To: , , , , , , , CC: , , , Sean Wang Subject: [PATCH v2 04/30] arm: dts: mt7623: add subsystem clock controller device nodes Date: Wed, 26 Apr 2017 17:25:48 +0800 Message-ID: <1493198774-4478-5-git-send-email-sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com> References: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Crispin Add MT7623 subsystem clock controllers for hifsys and ethsys. Signed-off-by: John Crispin Signed-off-by: Sean Wang --- arch/arm/boot/dts/mt7623.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index b97b2ba..54cff6a 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -190,4 +190,20 @@ clock-names = "baud", "bus"; status = "disabled"; }; + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "mediatek,mt2701-hifsys", + "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7623-ethsys", + "mediatek,mt2701-ethsys", + "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; }; -- 1.9.1