[PATCH v2 0/4] Add support for ThunderX2 pmu events using json files

[PATCH v2 0/4] Add support for ThunderX2 pmu events using json files

[Ganapatrao Kulkarni]

Extending json/jevent framework for parsing arm64 event files.
Adding jevents for ThunderX2 implementation defined PMU events.

v2:
   - Updated as per Mark Rutland's suggestions.
   - added provision for get_cpuid_str to get cpu id string
     from associated cpus of pmu core device.

v1: Initial patchset.

Ganapatrao Kulkarni (4):
  perf utils: passing pmu as a parameter to function get_cpuid_str
  perf tools arm64: Add support for get_cpuid_str function.
  perf utils: Add helper function is_pmu_core to detect PMU CORE devices
  perf vendor events arm64: Add implementation defined pmu core events
    of ThunderX2

 tools/perf/arch/arm64/util/Build                   |  1 +
 tools/perf/arch/arm64/util/header.c                | 41 ++++++++++++++
 tools/perf/arch/powerpc/util/header.c              |  3 +-
 tools/perf/arch/x86/util/header.c                  |  4 +-
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 14 +++++
 .../arm64/thunderx2/implementation-defined.json    | 62 ++++++++++++++++++++++
 tools/perf/util/header.h                           |  3 +-
 tools/perf/util/pmu.c                              | 54 ++++++++++++++++---
 8 files changed, 171 insertions(+), 11 deletions(-)
 create mode 100644 tools/perf/arch/arm64/util/header.c
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json

-- 
1.8.1.4

[PATCH v2 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

[Ganapatrao Kulkarni]

cpuid string will not be same on all CPUs on heterogeneous
platforms like ARM's big.LITTLE, adding provision(using pmu->cpus)
to find cpuid string from associated CPUs of PMU CORE device.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/arch/powerpc/util/header.c |  3 ++-
 tools/perf/arch/x86/util/header.c     |  4 +++-
 tools/perf/util/header.h              |  3 ++-
 tools/perf/util/pmu.c                 | 10 ++++++----
 4 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c
index 9aaa6f5..9a70cc1 100644
--- a/tools/perf/arch/powerpc/util/header.c
+++ b/tools/perf/arch/powerpc/util/header.c
@@ -34,10 +34,11 @@
 }
 
 char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu)
 {
 	char *bufp;
 
+	do { if (pmu) {} } while (0);
 	if (asprintf(&bufp, "%.8lx", mfspr(SPRN_PVR)) < 0)
 		bufp = NULL;
 
diff --git a/tools/perf/arch/x86/util/header.c b/tools/perf/arch/x86/util/header.c
index a74a48d..1e240ca 100644
--- a/tools/perf/arch/x86/util/header.c
+++ b/tools/perf/arch/x86/util/header.c
@@ -65,10 +65,12 @@
 }
 
 char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu)
 {
 	char *buf = malloc(128);
 
+	do { if (pmu) {} } while (0);
+
 	if (__get_cpuid(buf, 128, "%s-%u-%X$") < 0) {
 		free(buf);
 		return NULL;
diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h
index d30109b..6bb14a4 100644
--- a/tools/perf/util/header.h
+++ b/tools/perf/util/header.h
@@ -8,6 +8,7 @@
 #include <linux/types.h>
 #include "event.h"
 #include "env.h"
+#include "pmu.h"
 
 enum {
 	HEADER_RESERVED		= 0,	/* always cleared */
@@ -151,5 +152,5 @@ int perf_event__process_build_id(struct perf_tool *tool,
  */
 int get_cpuid(char *buffer, size_t sz);
 
-char *get_cpuid_str(void);
+char *get_cpuid_str(struct perf_pmu *pmu);
 #endif /* __PERF_HEADER_H */
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 12f84dd..c754805 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -504,8 +504,9 @@ static struct cpu_map *pmu_cpumask(const char *name)
  * Each architecture should provide a more precise id string that
  * can be use to match the architecture's "mapfile".
  */
-char * __weak get_cpuid_str(void)
+char * __weak get_cpuid_str(struct perf_pmu *pmu)
 {
+	do { if (pmu) {} } while (0);
 	return NULL;
 }
 
@@ -514,7 +515,8 @@ char * __weak get_cpuid_str(void)
  * to the current running CPU. Then, add all PMU events from that table
  * as aliases.
  */
-static void pmu_add_cpu_aliases(struct list_head *head, const char *name)
+static void pmu_add_cpu_aliases(struct list_head *head, const char *name,
+		struct perf_pmu *pmu)
 {
 	int i;
 	struct pmu_events_map *map;
@@ -526,7 +528,7 @@ static void pmu_add_cpu_aliases(struct list_head *head, const char *name)
 	if (cpuid)
 		cpuid = strdup(cpuid);
 	if (!cpuid)
-		cpuid = get_cpuid_str();
+		cpuid = get_cpuid_str(pmu);
 	if (!cpuid)
 		return;
 
@@ -601,12 +603,12 @@ static struct perf_pmu *pmu_lookup(const char *name)
 	if (pmu_aliases(name, &aliases))
 		return NULL;
 
-	pmu_add_cpu_aliases(&aliases, name);
 	pmu = zalloc(sizeof(*pmu));
 	if (!pmu)
 		return NULL;
 
 	pmu->cpus = pmu_cpumask(name);
+	pmu_add_cpu_aliases(&aliases, name, pmu);
 
 	INIT_LIST_HEAD(&pmu->format);
 	INIT_LIST_HEAD(&pmu->aliases);
-- 
1.8.1.4

[PATCH v2 2/4] perf tools arm64: Add support for get_cpuid_str function.

[Ganapatrao Kulkarni]

function get_cpuid_str returns MIDR string of the first online
cpu from the range of cpus associated with the pmu core device.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/arch/arm64/util/Build    |  1 +
 tools/perf/arch/arm64/util/header.c | 41 +++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 tools/perf/arch/arm64/util/header.c

diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index cef6fb3..b1ab72d 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,3 +1,4 @@
+libperf-y += header.o
 libperf-$(CONFIG_DWARF)     += dwarf-regs.o
 libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
 
diff --git a/tools/perf/arch/arm64/util/header.c b/tools/perf/arch/arm64/util/header.c
new file mode 100644
index 0000000..d8980a6b
--- /dev/null
+++ b/tools/perf/arch/arm64/util/header.c
@@ -0,0 +1,41 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "header.h"
+
+#define LINUX_SYS_CPU_DIRECTORY "/sys/devices/system/cpu/"
+#define MIDR "/regs/identification/midr_el1"
+
+char *get_cpuid_str(struct perf_pmu *pmu)
+{
+	char *buf = malloc(128);
+	FILE *file;
+	char *ret = NULL;
+	int cpu;
+	char sys_file[256];
+	struct cpu_map *cpus;
+
+	if (!pmu->cpus)
+		return NULL;
+
+	/* read midr from list of cpus mapped to this pmu */
+	cpus = cpu_map__get(pmu->cpus);
+
+	for (cpu = 0; cpu < cpus->nr; cpu++) {
+		sprintf(sys_file, LINUX_SYS_CPU_DIRECTORY"cpu%d"MIDR,
+				cpus->map[cpu]);
+		file = fopen(sys_file, "r");
+		if (file) {
+			ret = fgets(buf, 128, file);
+			if (ret) {
+				buf[strlen(buf)-1] = '\0';
+				fclose(file);
+				cpu_map__put(cpus);
+				return buf;
+			}
+			fclose(file);
+		}
+	}
+	cpu_map__put(cpus);
+	free(buf);
+	return ret;
+}
-- 
1.8.1.4

[PATCH v2 3/4] perf utils: Add helper function is_pmu_core to detect PMU CORE devices

[Ganapatrao Kulkarni]

On some platforms, PMU core devices sysfs name is not cpu.
Adding function is_pmu_core to detect as core device using
core device specific hints in sysfs.

For arm64 platforms, all core devices have file "cpus" in sysfs.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/util/pmu.c | 44 ++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index c754805..48333fe 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -499,6 +499,39 @@ static struct cpu_map *pmu_cpumask(const char *name)
 }
 
 /*
+ *  PMU CORE devices have different name other than cpu in sysfs on some
+ *  platforms. looking for possible sysfs files to identify as core device.
+ */
+static int is_pmu_core(const char *name)
+{
+	struct stat st;
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+	const char **template;
+	const char *templates[] = {
+		 "%s/bus/event_source/devices/%s/cpus",
+		 NULL
+	};
+
+	if (!sysfs)
+		return 0;
+
+	/* Look for cpu sysfs */
+	snprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
+	if ((stat(path, &st) == 0) &&
+			(strncmp(name, "cpu", strlen("cpu")) == 0))
+		return 1;
+
+	for (template = templates; *template; template++) {
+		snprintf(path, PATH_MAX, *template, sysfs, name);
+		if (stat(path, &st) == 0)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
  * Return the CPU id as a raw string.
  *
  * Each architecture should provide a more precise id string that
@@ -552,15 +585,18 @@ static void pmu_add_cpu_aliases(struct list_head *head, const char *name,
 	 */
 	i = 0;
 	while (1) {
-		const char *pname;
 
 		pe = &map->table[i++];
 		if (!pe->name)
 			break;
 
-		pname = pe->pmu ? pe->pmu : "cpu";
-		if (strncmp(pname, name, strlen(pname)))
-			continue;
+		if (!is_pmu_core(name)) {
+			/* check for uncore devices */
+			if (pe->pmu == NULL)
+				continue;
+			if (strncmp(pe->pmu, name, strlen(pe->pmu)))
+				continue;
+		}
 
 		/* need type casts to override 'const' */
 		__perf_pmu__new_alias(head, NULL, (char *)pe->name,
-- 
1.8.1.4

[PATCH v2 4/4] perf vendor events arm64: Add implementation defined pmu core events of ThunderX2

[Ganapatrao Kulkarni]

This is not a full event list, but a short list of useful events.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 14 +++++
 .../arm64/thunderx2/implementation-defined.json    | 62 ++++++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json

diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
new file mode 100644
index 0000000..bc9f798
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -0,0 +1,14 @@
+# Format:
+#	MIDR,Version,JSON/file/pathname,Type
+#
+# where
+#	MIDR	Processor version
+#	Version could be used to track version of of JSON file
+#		but currently unused.
+#	JSON/file/pathname is the path to JSON file, relative
+#		to tools/perf/pmu-events/arch/arm64/.
+#	Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
+0x00000000420f5161,v1,thunderx2,core
diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
new file mode 100644
index 0000000..cdb03db
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
@@ -0,0 +1,62 @@
+[
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, read",
+        "EventCode": "0x40",
+        "EventName": "l1d_cache_access_read",
+        "BriefDescription": "l1d cache access, read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, write ",
+        "EventCode": "0x41",
+        "EventName": "l1d_cache_access_write",
+        "BriefDescription": "l1d cache access, write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, read",
+        "EventCode": "0x42",
+        "EventName": "l1d_cache_refill_read",
+        "BriefDescription": "l1d cache refill, read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, write",
+        "EventCode": "0x43",
+        "EventName": "l1d_cache_refill_write",
+        "BriefDescription": "l1d refill, write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, read",
+        "EventCode": "0x4C",
+        "EventName": "l1d_tlb_refill_read",
+        "BriefDescription": "l1d tlb refill, read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, write",
+        "EventCode": "0x4D",
+        "EventName": "l1d_tlb_refill_write",
+        "BriefDescription": "l1d tlb refill, write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+        "EventCode": "0x4E",
+        "EventName": "l1d_tlb_read",
+        "BriefDescription": "l1d tlb, read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+        "EventCode": "0x4F",
+        "EventName": "l1d_tlb_write",
+        "BriefDescription": "l1d tlb, write",
+    },
+    {
+        "PublicDescription": "Bus access, read",
+        "EventCode": "0x60",
+        "EventName": "bus_access_read",
+        "BriefDescription": "Bus access, read",
+   },
+   {
+        "PublicDescription": "Bus access, write",
+        "EventCode": "0x61",
+        "EventName": "bus_access_write",
+        "BriefDescription": "Bus access, write",
+   }
+]
-- 
1.8.1.4

Re: [PATCH v2 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

[Jayachandran C]

On Fri, Apr 28, 2017 at 10:23:44AM +0530, Ganapatrao Kulkarni wrote:
> cpuid string will not be same on all CPUs on heterogeneous
> platforms like ARM's big.LITTLE, adding provision(using pmu->cpus)
> to find cpuid string from associated CPUs of PMU CORE device.
> 
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> ---
>  tools/perf/arch/powerpc/util/header.c |  3 ++-
>  tools/perf/arch/x86/util/header.c     |  4 +++-
>  tools/perf/util/header.h              |  3 ++-
>  tools/perf/util/pmu.c                 | 10 ++++++----
>  4 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c
> index 9aaa6f5..9a70cc1 100644
> --- a/tools/perf/arch/powerpc/util/header.c
> +++ b/tools/perf/arch/powerpc/util/header.c
> @@ -34,10 +34,11 @@
>  }
>  
>  char *
> -get_cpuid_str(void)
> +get_cpuid_str(struct perf_pmu *pmu)
>  {
>  	char *bufp;
>  
> +	do { if (pmu) {} } while (0);

If this is to avoid warnings, can you use __maybe_unused here?

JC.

Re: [PATCH v2 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

[Ganapatrao Kulkarni]

On Fri, Apr 28, 2017 at 2:38 PM, Jayachandran C
<jnair@caviumnetworks.com> wrote:
> On Fri, Apr 28, 2017 at 10:23:44AM +0530, Ganapatrao Kulkarni wrote:
>> cpuid string will not be same on all CPUs on heterogeneous
>> platforms like ARM's big.LITTLE, adding provision(using pmu->cpus)
>> to find cpuid string from associated CPUs of PMU CORE device.
>>
>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>> ---
>>  tools/perf/arch/powerpc/util/header.c |  3 ++-
>>  tools/perf/arch/x86/util/header.c     |  4 +++-
>>  tools/perf/util/header.h              |  3 ++-
>>  tools/perf/util/pmu.c                 | 10 ++++++----
>>  4 files changed, 13 insertions(+), 7 deletions(-)
>>
>> diff --git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c
>> index 9aaa6f5..9a70cc1 100644
>> --- a/tools/perf/arch/powerpc/util/header.c
>> +++ b/tools/perf/arch/powerpc/util/header.c
>> @@ -34,10 +34,11 @@
>>  }
>>
>>  char *
>> -get_cpuid_str(void)
>> +get_cpuid_str(struct perf_pmu *pmu)
>>  {
>>       char *bufp;
>>
>> +     do { if (pmu) {} } while (0);
>
> If this is to avoid warnings, can you use __maybe_unused here?

thanks, i will do.
>
> JC.

thanks
Ganapat

Re: [PATCH v2 4/4] perf vendor events arm64: Add implementation defined pmu core events of ThunderX2

[Will Deacon]

On Fri, Apr 28, 2017 at 10:23:47AM +0530, Ganapatrao Kulkarni wrote:
> This is not a full event list, but a short list of useful events.
> 
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> ---
>  tools/perf/pmu-events/arch/arm64/mapfile.csv       | 14 +++++
>  .../arm64/thunderx2/implementation-defined.json    | 62 ++++++++++++++++++++++
>  2 files changed, 76 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
>  create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> new file mode 100644
> index 0000000..bc9f798
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -0,0 +1,14 @@
> +# Format:
> +#	MIDR,Version,JSON/file/pathname,Type
> +#
> +# where
> +#	MIDR	Processor version
> +#	Version could be used to track version of of JSON file
> +#		but currently unused.
> +#	JSON/file/pathname is the path to JSON file, relative
> +#		to tools/perf/pmu-events/arch/arm64/.
> +#	Type is core, uncore etc
> +#
> +#
> +#Family-model,Version,Filename,EventType
> +0x00000000420f5161,v1,thunderx2,core

In general, I don't think we want to require an exact match on the whole
MIDR here. Specifically, we'd want to mask out the Variant and Revision
fields for ARM CPUs, to avoid having to update the mapfile all the time.

Is it possible to support wildcarding in the MIDR match?

Will

Re: [PATCH v2 4/4] perf vendor events arm64: Add implementation defined pmu core events of ThunderX2

[Ganapatrao Kulkarni]

On Fri, Apr 28, 2017 at 10:50 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Fri, Apr 28, 2017 at 10:23:47AM +0530, Ganapatrao Kulkarni wrote:
>> This is not a full event list, but a short list of useful events.
>>
>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>> ---
>>  tools/perf/pmu-events/arch/arm64/mapfile.csv       | 14 +++++
>>  .../arm64/thunderx2/implementation-defined.json    | 62 ++++++++++++++++++++++
>>  2 files changed, 76 insertions(+)
>>  create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
>>  create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
>>
>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>> new file mode 100644
>> index 0000000..bc9f798
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>> @@ -0,0 +1,14 @@
>> +# Format:
>> +#    MIDR,Version,JSON/file/pathname,Type
>> +#
>> +# where
>> +#    MIDR    Processor version
>> +#    Version could be used to track version of of JSON file
>> +#            but currently unused.
>> +#    JSON/file/pathname is the path to JSON file, relative
>> +#            to tools/perf/pmu-events/arch/arm64/.
>> +#    Type is core, uncore etc
>> +#
>> +#
>> +#Family-model,Version,Filename,EventType
>> +0x00000000420f5161,v1,thunderx2,core
>
> In general, I don't think we want to require an exact match on the whole
> MIDR here. Specifically, we'd want to mask out the Variant and Revision
> fields for ARM CPUs, to avoid having to update the mapfile all the time.
>
> Is it possible to support wildcarding in the MIDR match?

thanks, Variant and Revision can be wildcard.
>
> Will

thanks
Ganapat