From: Scott Wood <oss@buserror.net>
To: christophe leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO
Date: Mon, 01 May 2017 13:14:21 -0500 [thread overview]
Message-ID: <1493662461.25397.29.camel@buserror.net> (raw)
In-Reply-To: <b0129071-0b09-a357-d262-19cf335f8224@c-s.fr>
On Mon, 2017-05-01 at 09:46 +0200, christophe leroy wrote:
>
> Le 30/04/2017 à 08:48, Scott Wood a écrit :
> > On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote:
> > >
> > > @@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np)
> > >
> > > spin_lock_init(&cpm1_gc->lock);
> > >
> > > + if (!of_property_read_u16(np, "interrupts-mask", &mask)) {
> > > + int i, j;
> > > +
> > > + for (i = 0, j = 0; i < 16; i++)
> > > + if (mask & (1 << (15 - i)))
> > > + cpm1_gc->irq[i] =
> > > irq_of_parse_and_map(np, j++);
> > > + }
> >
> > Do we really need to use MSB-first bit numbering here?
>
> Well, I think it is better to keep the GPIOs in the same order as in the
> CPM1 registers, like everywhere else in that driver, isn't it ?
>
> The registers have GPIO 0 in the MSB and GPIO15 in the LSB.
OK, if there's a specific register this is reflecting that's reasonable.
-Scott
prev parent reply other threads:[~2017-05-01 18:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-09 9:42 [PATCH] powerpc/8xx: Adding support of IRQ in MPC8xx GPIO Christophe Leroy
2017-04-30 6:48 ` Scott Wood
2017-05-01 7:46 ` christophe leroy
2017-05-01 18:14 ` Scott Wood [this message]
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