From: Xiaochen Shen <xiaochen.shen@intel.com>
To: tglx@linutronix.de, linux-kernel@vger.kernel.org, x86@kernel.org
Cc: vikas.shivappa@linux.intel.com, tony.luck@intel.com,
Xiaochen Shen <xiaochen.shen@intel.com>,
Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH] x86/intel_rdt: Fix a typo in Documentation
Date: Wed, 3 May 2017 11:15:56 +0800 [thread overview]
Message-ID: <1493781356-24229-1-git-send-email-xiaochen.shen@intel.com> (raw)
The typo is in example 3.
"C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
6-7 instead of wanted core 4-7.
Correct this typo to avoid confusion.
Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
Documentation/x86/intel_rdt_ui.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt
index 0f6d847..c491a1b 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -295,7 +295,7 @@ kernel and the tasks running there get 50% of the cache. They should
also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
siblings and only the real time threads are scheduled on the cores 4-7.
-# echo C0 > p0/cpus
+# echo F0 > p0/cpus
4) Locking between applications
--
1.8.3.1
next reply other threads:[~2017-05-03 3:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-03 3:15 Xiaochen Shen [this message]
2017-05-09 7:03 ` [PATCH] x86/intel_rdt: Fix a typo in Documentation Thomas Gleixner
2017-05-09 7:19 ` Xiaochen Shen
2017-05-09 7:22 ` Thomas Gleixner
2017-05-09 7:38 ` Xiaochen Shen
2017-05-09 7:45 ` [tip:x86/urgent] " tip-bot for Xiaochen Shen
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