From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751310AbdFFGIH (ORCPT ); Tue, 6 Jun 2017 02:08:07 -0400 Received: from mga07.intel.com ([134.134.136.100]:27411 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751165AbdFFGIF (ORCPT ); Tue, 6 Jun 2017 02:08:05 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,304,1493708400"; d="scan'208";a="270668203" Message-ID: <1496729283.24288.83.camel@ranerica-desktop> Subject: Re: [PATCH v7 05/26] x86/mpx: Do not use SIB.base if its value is 101b and ModRM.mod = 0 From: Ricardo Neri To: Borislav Petkov Cc: Ingo Molnar , Thomas Gleixner , "H. Peter Anvin" , Andy Lutomirski , Borislav Petkov , Peter Zijlstra , Andrew Morton , Brian Gerst , Chris Metcalf , Dave Hansen , Paolo Bonzini , Liang Z Li , Masami Hiramatsu , Huang Rui , Jiri Slaby , Jonathan Corbet , "Michael S. Tsirkin" , Paul Gortmaker , Vlastimil Babka , Chen Yucong , Alexandre Julliard , Stas Sergeev , Fenghua Yu , "Ravi V. Shankar" , Shuah Khan , linux-kernel@vger.kernel.org, x86@kernel.org, linux-msdos@vger.kernel.org, wine-devel@winehq.org, Adam Buchbinder , Colin Ian King , Lorenzo Stoakes , Qiaowei Ren , Nathan Howard , Adan Hawthorn , Joe Perches Date: Mon, 05 Jun 2017 23:08:03 -0700 In-Reply-To: <20170529130709.7hv6act6lgoaj5po@pd.tnic> References: <20170505181724.55000-1-ricardo.neri-calderon@linux.intel.com> <20170505181724.55000-6-ricardo.neri-calderon@linux.intel.com> <20170529130709.7hv6act6lgoaj5po@pd.tnic> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-05-29 at 15:07 +0200, Borislav Petkov wrote: > On Fri, May 05, 2017 at 11:17:03AM -0700, Ricardo Neri wrote: > > Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software > > Developer's Manual volume 2A states that when a SIB byte is used and the > > base of the SIB byte points is base = 101b and the mod part > > of the ModRM byte is zero, the base port on the effective address > > computation is null. In this case, a 32-bit displacement follows the SIB > > byte. This is obtained when the instruction decoder parses the operands. > > > > To signal this scenario, a -EDOM error is returned to indicate callers that > > they should ignore the base. > > > > Cc: Borislav Petkov > > Cc: Andy Lutomirski > > Cc: Dave Hansen > > Cc: Adam Buchbinder > > Cc: Colin Ian King > > Cc: Lorenzo Stoakes > > Cc: Qiaowei Ren > > Cc: Peter Zijlstra > > Cc: Nathan Howard > > Cc: Adan Hawthorn > > Cc: Joe Perches > > Cc: Ravi V. Shankar > > Cc: x86@kernel.org > > Signed-off-by: Ricardo Neri > > --- > > arch/x86/mm/mpx.c | 27 ++++++++++++++++++++------- > > 1 file changed, 20 insertions(+), 7 deletions(-) > > > > diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c > > index 7397b81..30aef92 100644 > > --- a/arch/x86/mm/mpx.c > > +++ b/arch/x86/mm/mpx.c > > @@ -122,6 +122,15 @@ static int get_reg_offset(struct insn *insn, struct pt_regs *regs, > > > > case REG_TYPE_BASE: > > regno = X86_SIB_BASE(insn->sib.value); > > + /* > > + * If ModRM.mod is 0 and SIB.base == 5, the base of the > > + * register-indirect addressing is 0. In this case, a > > + * 32-bit displacement is expected in this case; the > > + * instruction decoder finds such displacement for us. > > That last sentence reads funny. Just say: > > "In this case, a 32-bit displacement follows the SIB byte." Agreed. I will update the comment to make more sense. Thanks and BR, Ricardo