From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755832AbdGKOyJ (ORCPT ); Tue, 11 Jul 2017 10:54:09 -0400 Received: from mail-ve1eur01on0101.outbound.protection.outlook.com ([104.47.1.101]:45416 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755310AbdGKOyI (ORCPT ); Tue, 11 Jul 2017 10:54:08 -0400 From: Marcel Ziswiler To: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "contact@paulk.fr" , "linux-tegra@vger.kernel.org" CC: "jonathanh@nvidia.com" , "mperttunen@nvidia.com" , "treding@nvidia.com" , "swarren@nvidia.com" Subject: Re: [PATCH] ARM: tegra: Register host1x node with iommu binding on tegra124 Thread-Topic: [PATCH] ARM: tegra: Register host1x node with iommu binding on tegra124 Thread-Index: AQHS+lWK79IETD7mPUijO21AjmqbNw== Date: Tue, 11 Jul 2017 14:54:04 +0000 Message-ID: <1499784841.1520.20.camel@toradex.com> References: <20170709163614.6746-1-contact@paulk.fr> <1499763009.1340.11.camel@paulk.fr> In-Reply-To: <1499763009.1340.11.camel@paulk.fr> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: lists.infradead.org; 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spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" Content-ID: <95BC908727B53F47952B8ACF0AD2C193@eurprd05.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2017 14:54:04.3416 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB1881 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v6BEsPo1017082 On Tue, 2017-07-11 at 11:50 +0300, Paul Kocialkowski wrote: > On Sun, 2017-07-09 at 19:36 +0300, Paul Kocialkowski wrote: > > This registers the host1x node with the SMMU (as HC swgroup) to > > allow > > the host1x code to attach to it. It avoid failing the probe > > sequence, > > which resulted in the tegra drm driver not probing and thus nothing > > being displayed on-screen. > > Fixes: 404bfb78daf3 ("gpu: host1x: Add IOMMU support") > > > Signed-off-by: Paul Kocialkowski > W9ppeneeCTY@public.gmane.org> Tested-by: Marcel Ziswiler Tested-on: Apalis TK1, Jetson-TK1 > > --- > >  arch/arm/boot/dts/tegra124.dtsi | 1 + > >  1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/boot/dts/tegra124.dtsi > > b/arch/arm/boot/dts/tegra124.dtsi > > index 187a36c6d0fc..b3b89befffeb 100644 > > --- a/arch/arm/boot/dts/tegra124.dtsi > > +++ b/arch/arm/boot/dts/tegra124.dtsi > > @@ -85,6 +85,7 @@ > >   clocks = <&tegra_car TEGRA124_CLK_HOST1X>; > >   resets = <&tegra_car 28>; > >   reset-names = "host1x"; > > + iommus = <&mc TEGRA_SWGROUP_HC>; > >   > >   #address-cells = <2>; > >   #size-cells = <2>; So I take it we still will need this one moving forward, correct? How about tegra30, I guess the same applies there, isn't it? Should I send a patch or are you guys doing that?