From: Vignesh Raghavendra <vigneshr@ti.com>
To: <Tudor.Ambarus@microchip.com>, <boris.brezillon@collabora.com>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 13/20] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
Date: Tue, 5 Nov 2019 22:37:10 +0530 [thread overview]
Message-ID: <14e9c474-1a92-b8be-12cf-56c7f6d0d696@ti.com> (raw)
In-Reply-To: <20191102112316.20715-14-tudor.ambarus@microchip.com>
On 02-Nov-19 4:53 PM, Tudor.Ambarus@microchip.com wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Make sure that when doing a lock() or an unlock() operation we don't clear
> the QE bit from Status Register 2.
>
> JESD216 revB or later offers information about the *default* Status
> Register commands to use (see BFPT DWORDS[15], bits 22:20). In this
> standard, Status Register 1 refers to the first data byte transferred on a
> Read Status (05h) or Write Status (01h) command. Status register 2 refers
> to the byte read using instruction 35h. Status register 2 is the second
> byte transferred in a Write Status (01h) command.
>
> Industry naming and definitions of these Status Registers may differ.
> The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20.
> There are cases in which writing only one byte to the Status Register 1
> has the side-effect of clearing Status Register 2 and implicitly the Quad
> Enable bit. This side-effect is hit just by the
> BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases.
>
But I see that 1 byte SR1 write still happens as part of
spi_nor_clear_sr_bp() until patch 20/20. So is this only a partial fix?
Should this patch be rearranged to appear along with 20/20?
> Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 120 ++++++++++++++++++++++++++++++++++++++++--
> include/linux/mtd/spi-nor.h | 3 ++
> 2 files changed, 118 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 725dab241271..f96bc80c0ed1 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -959,12 +959,19 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
> return spi_nor_wait_till_ready(nor);
> }
>
[...]
> +/**
> * spi_nor_write_sr2() - Write the Status Register 2 using the
> * SPINOR_OP_WRSR2 (3eh) command.
> * @nor: pointer to 'struct spi_nor'.
> @@ -3634,19 +3723,38 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
> + /*
> + * Writing only one byte to the Status Register has the
> + * side-effect of clearing Status Register 2.
> + */
> case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
> + /*
> + * Read Configuration Register (35h) instruction is not
> + * supported.
> + */
> + nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
Since SNOR_F_HAS_16BIT_SR is set by default in
spi_nor_info_init_params(), no need to set the flag here again
> params->quad_enable = spansion_no_read_cr_quad_enable;
> break;
>
> case BFPT_DWORD15_QER_SR1_BIT6:
> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> params->quad_enable = macronix_quad_enable;
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT7:
> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> params->quad_enable = sr2_bit7_quad_enable;
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT1:
> + /*
> + * JESD216 rev B or later does not specify if writing only one
> + * byte to the Status Register clears or not the Status
> + * Register 2, so let's be cautious and keep the default
> + * assumption of a 16-bit Write Status (01h) command.
> + */
> + nor->flags |= SNOR_F_HAS_16BIT_SR;
> +
Same here...
> params->quad_enable = spansion_read_cr_quad_enable;
> break;
>
> @@ -4613,6 +4721,8 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
> params->quad_enable = spansion_read_cr_quad_enable;
> params->set_4byte = spansion_set_4byte;
> params->setup = spi_nor_default_setup;
> + /* Default to 16-bit Write Status (01h) Command */
> + nor->flags |= SNOR_F_HAS_16BIT_SR;
>
> /* Set SPI NOR sizes. */
> params->size = (u64)info->sector_size * info->n_sectors;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index d1d736d3c8ab..d6ec55cc6d97 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -243,6 +243,9 @@ enum spi_nor_option_flags {
> SNOR_F_4B_OPCODES = BIT(6),
> SNOR_F_HAS_4BAIT = BIT(7),
> SNOR_F_HAS_LOCK = BIT(8),
> + SNOR_F_HAS_16BIT_SR = BIT(9),
> + SNOR_F_NO_READ_CR = BIT(10),
> +
> };
>
> /**
>
next prev parent reply other threads:[~2019-11-05 17:07 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-02 11:23 [PATCH v4 00/20] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 01/20] mtd: spi-nor: Use dev_dbg insted of dev_err for low level info Tudor.Ambarus
2019-11-05 12:12 ` Vignesh Raghavendra
2019-11-06 7:07 ` Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 02/20] mtd: spi-nor: Print debug info inside Reg Ops methods Tudor.Ambarus
2019-11-05 12:13 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Tudor.Ambarus
2019-11-06 9:19 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 04/20] mtd: spi-nor: Rename label as it is no longer generic Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 05/20] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 06/20] mtd: spi-nor: Move the WE and wait calls inside Write SR methods Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 07/20] mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 08/20] mtd: spi-nor: Describe all the Reg Ops Tudor.Ambarus
2019-11-05 12:21 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-11-05 12:35 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 10/20] mtd: spi-nor: Fix errno on Quad Enable methods Tudor.Ambarus
2019-11-05 12:36 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 11/20] mtd: spi-nor: Check all the bits written, not just the BP ones Tudor.Ambarus
2019-11-05 12:21 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 12/20] mtd: spi-nor: Print debug message when the read back test fails Tudor.Ambarus
2019-11-05 12:37 ` Vignesh Raghavendra
2019-11-06 7:24 ` Tudor.Ambarus
2019-11-06 7:39 ` Vignesh Raghavendra
2019-11-07 5:58 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 13/20] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-11-05 17:07 ` Vignesh Raghavendra [this message]
2019-11-06 8:33 ` Tudor.Ambarus
2019-11-06 16:26 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 14/20] mtd: spi-nor: Extend the QE Read Back test to the entire SR byte Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 15/20] mtd: spi-nor: Extend the QE Read Back test to both SR1 and SR2 Tudor.Ambarus
2019-11-05 16:06 ` Vignesh Raghavendra
2019-11-06 8:41 ` Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 16/20] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Tudor.Ambarus
2019-11-06 5:45 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 17/20] mtd: spi-nor: Merge spansion Quad Enable methods Tudor.Ambarus
2019-11-06 5:46 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Tudor.Ambarus
2019-11-06 6:00 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 19/20] mtd: spi-nor: Prepend "spi_nor_" to "sr2_bit7_quad_enable" Tudor.Ambarus
2019-11-02 11:24 ` [PATCH v4 20/20] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-11-07 6:27 ` [PATCH v4 00/20] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
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