From: Varadarajan Narayanan <varada@codeaurora.org>
To: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
svarbanov@mm-sol.com, kishon@ti.com, sboyd@codeaurora.org,
vivek.gautam@codeaurora.org, fengguang.wu@intel.com,
weiyongjun1@huawei.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org
Cc: Varadarajan Narayanan <varada@codeaurora.org>
Subject: [PATCH v3 2/8] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Date: Thu, 20 Jul 2017 11:04:34 +0530 [thread overview]
Message-ID: <1500528880-25804-3-git-send-email-varada@codeaurora.org> (raw)
In-Reply-To: <1500528880-25804-1-git-send-email-varada@codeaurora.org>
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 5d7a51f..82fe0c4 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
Required properties:
- compatible: compatible list, contains:
+ "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
@@ -38,6 +39,8 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
+ For "qcom,ipq8074-qmp-pcie-phy" must contain:
+ "phy", "phy_phy".
- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node:
- clock-output-names: Name of the phy clock that will be the parent for
the above pipe clock.
+ For "qcom,ipq8074-qmp-pcie-phy":
+ - "pcie20_phy0_pipe_clk" Pipe Clock parent
+ (or)
+ "pcie20_phy1_pipe_clk"
+
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
- reset-names: Must contain following for pcie qmp phys:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-07-20 5:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 1/8] dt-bindings: phy: qmp: Add output-clock-names Varadarajan Narayanan
2017-07-20 5:34 ` Varadarajan Narayanan [this message]
2017-07-20 5:34 ` [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name Varadarajan Narayanan
2017-07-21 8:01 ` Vivek Gautam
2017-07-20 5:34 ` [PATCH v3 4/8] phy: qcom-qmp: Handle unavailable registers Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 5/8] phy: qcom-qmp: Add support for IPQ8074 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 6/8] PCI: dwc: qcom: Use block IP version for operations Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 7/8] dt-bindings: pci: qcom: Add support for IPQ8074 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 8/8] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller Varadarajan Narayanan
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