From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751751AbdG0PK5 (ORCPT ); Thu, 27 Jul 2017 11:10:57 -0400 Received: from foss.arm.com ([217.140.101.70]:48116 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751684AbdG0PKx (ORCPT ); Thu, 27 Jul 2017 11:10:53 -0400 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, will.deacon@arm.com, marc.zyngier@arm.com, mark.rutland@arm.com, sudeep.holla@arm.com, mathieu.poirier@linaro.org, Jonathan.Cameron@huawei.com, Suzuki K Poulose , Rob Herring Subject: [PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU Date: Thu, 27 Jul 2017 16:10:17 +0100 Message-Id: <1501168218-26741-6-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1501168218-26741-1-git-send-email-suzuki.poulose@arm.com> References: <1501168218-26741-1-git-send-email-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland Cc: Will Deacon Cc: Rob Herring Signed-off-by: Suzuki K Poulose --- .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt new file mode 100644 index 0000000..b9935ac --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt @@ -0,0 +1,27 @@ +* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores +with a shared L3 memory system, control logic and external interfaces to +form a multicore cluster. The PMU enables to gather various statistics on +the operations of the DSU. The PMU provides independent 32bit counters that +can count any of the supported events, along with a 64bit cycle counter. +The PMU is accessed via CPU system registers and has no MMIO component. + +** DSU PMU required properties: + +- compatible : should be one of : + + "arm,dsu-pmu" + +- interrupts : Exactly 1 SPI must be listed. + +- cpus : List of phandles for the CPUs connected to this DSU instance. + + +** Example: + +dsu_pmu@0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu_0>, <&cpu_1>; +}; -- 2.7.5