From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751787AbdHAHED (ORCPT ); Tue, 1 Aug 2017 03:04:03 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:23165 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751737AbdHAHEB (ORCPT ); Tue, 1 Aug 2017 03:04:01 -0400 From: Erin Lo To: Matthias Brugger CC: , , , , , Chunfeng Yun , Erin Lo Subject: [PATCH 5/5] arm: dts: mt2701: Add usb3 device nodes Date: Tue, 1 Aug 2017 15:03:33 +0800 Message-ID: <1501571013-22327-6-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501571013-22327-1-git-send-email-erin.lo@mediatek.com> References: <1501571013-22327-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunfeng Yun Add xhci nodes and usb3 phy nodes for MT2701 Signed-off-by: Chunfeng Yun Signed-off-by: Erin Lo --- arch/arm/boot/dts/mt2701.dtsi | 79 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index efb5118..16242f5 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -677,6 +678,84 @@ #clock-cells = <1>; }; + usb0: usb@1a1c0000 { + compatible = "mediatek,mt8173-xhci"; + reg = <0 0x1a1c0000 0 0x1000>, + <0 0x1a1c4700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy0: usb-phy@1a1c4000 { + compatible = "mediatek,mt2701-u3phy"; + reg = <0 0x1a1c4000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb1: usb@1a240000 { + compatible = "mediatek,mt8173-xhci"; + reg = <0 0x1a240000 0 0x1000>, + <0 0x1a244700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: usb-phy@1a244000 { + compatible = "mediatek,mt2701-u3phy"; + reg = <0 0x1a244000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt2701-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; -- 1.9.1