From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752692AbdI1Rxs (ORCPT ); Thu, 28 Sep 2017 13:53:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50620 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752585AbdI1RvY (ORCPT ); Thu, 28 Sep 2017 13:51:24 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D1E4360C52 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Date: Thu, 28 Sep 2017 23:20:43 +0530 Message-Id: <1506621050-10129-7-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some of the Alpha PLL’s (like Spark, Brammo PLL) do not have CONFIG_CTL_U register. This patch adds the flag in properties for PLL’s which have CONFIG_CTL_U register and checks the same while doing PLL initial configuration. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 78eb6bf..b33d120 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -49,6 +49,9 @@ /* Returns the Alpha register width for pll type */ #define pll_alpha_width(type) (alpha_pll_props[type].alpha_width) +/* Returns the flags for pll type */ +#define pll_flags(type) (alpha_pll_props[type].flags) + /* Returns the alpha_pll_clk_ops for pll type */ #define pll_clk_ops(hw) (alpha_pll_props[to_clk_alpha_pll(hw)-> \ pll_type].ops) @@ -130,6 +133,9 @@ struct alpha_pll_clk_ops { struct alpha_pll_props { u8 reg_offsets[PLL_MAX_REGS]; u8 alpha_width; + +#define HAVE_64BIT_CONFIG_CTL BIT(0) + u8 flags; struct alpha_pll_clk_ops ops; }; @@ -180,7 +186,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, { u32 val, mask; u32 off = pll->offset; - u8 type = pll->pll_type; + u8 type = pll->pll_type, flags = pll_flags(type); regmap_write(regmap, off + pll_l(type), config->l); regmap_write(regmap, off + pll_alpha(type), config->alpha); @@ -188,6 +194,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_write(regmap, off + pll_cfg_ctl_u(type), config->config_ctl_hi_val); + if (flags & HAVE_64BIT_CONFIG_CTL) + regmap_write(regmap, off + pll_cfg_ctl_u(type), + config->config_ctl_hi_val); + val = config->main_output_mask; val |= config->aux_output_mask; val |= config->aux2_output_mask; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation