From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753889AbdJICn5 (ORCPT ); Sun, 8 Oct 2017 22:43:57 -0400 Received: from mailgw01.mediatek.com ([218.249.47.110]:35305 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753864AbdJICn4 (ORCPT ); Sun, 8 Oct 2017 22:43:56 -0400 X-UUID: d0f270607c4b489f94f4952fea381e3c-20171009 Message-ID: <1507517027.17567.42.camel@mhfsdcap03> Subject: Re: [PATCH 10/12] dt-bindings: usb: mtu3: add a optional property to disable u3ports From: Chunfeng Yun To: Rob Herring CC: Greg Kroah-Hartman , Felipe Balbi , Mathias Nyman , Matthias Brugger , Mark Rutland , Ian Campbell , , , , , Date: Mon, 9 Oct 2017 10:43:47 +0800 In-Reply-To: <20171005223117.23pvuzhg2th4byz3@rob-hp-laptop> References: <20171005223117.23pvuzhg2th4byz3@rob-hp-laptop> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2017-10-05 at 17:31 -0500, Rob Herring wrote: > On Thu, Sep 28, 2017 at 08:17:18AM +0800, Chunfeng Yun wrote: > > Add a new optional property to disable u3ports > > > > Signed-off-by: Chunfeng Yun > > --- > > .../devicetree/bindings/usb/mediatek,mtu3.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt > > index 49f5476..7c611d1 100644 > > --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt > > +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt > > @@ -44,6 +44,8 @@ Optional properties: > > - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode > > - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup > > control register, it depends on "mediatek,enable-wakeup". > > + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, > > + bit1 for u3port1, ... etc; > > How does this relate to the XHCI change? Same comment applies. There is a upper layer called IPPC (IP Power and Clock interface) shared by device IP and host IP (xHCI) to control power and clock of each port. So I can disable or enable xCHI's ports by IPPC indirectly.