From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3634C25B08 for ; Mon, 8 Aug 2022 05:22:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233263AbiHHFWG (ORCPT ); Mon, 8 Aug 2022 01:22:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230472AbiHHFWE (ORCPT ); Mon, 8 Aug 2022 01:22:04 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 901D3AE51; Sun, 7 Aug 2022 22:22:02 -0700 (PDT) X-UUID: d9445aa5bd2d4b018e3d6b324b5af82e-20220808 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=hQFOClsoBFUo+S5UAAJFv6gCUWt7W/fTQiotWmpTraQ=; b=hi4t5vLDn89nDFsJpoIkAnqReudoLKapkZaWWOdpmx/pmaDu+bswgEZbJAHU7BnExL6rf42bDuLsHTHtADRV5JxDKbfhWbcKmY0IaKS+yaUUmfORjVkHcogys6m0vj9VoPZkuGOAnpp84rFFxetFt2Yc5oSPIpm8TRvXyUwzer8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:ff16173d-2816-48e2-99db-879f28142fea,OB:0,LO B:30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,BULK:0,RULE:Release _Ham,ACTION:release,TS:45 X-CID-INFO: VERSION:1.1.9,REQID:ff16173d-2816-48e2-99db-879f28142fea,OB:0,LOB: 30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,BULK:0,RULE:Release_H am,ACTION:release,TS:45 X-CID-META: VersionHash:3d8acc9,CLOUDID:434bfc48-f57f-4088-93dd-066979cdb4e6,C OID:76cc9ae0fa5d,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:40,QS:nil,BEC:nil,COL:0 X-UUID: d9445aa5bd2d4b018e3d6b324b5af82e-20220808 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1586861012; Mon, 08 Aug 2022 13:21:57 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 8 Aug 2022 13:21:55 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 8 Aug 2022 13:21:55 +0800 Message-ID: <150988eef41cac1e1c4b422cf1ad65c10309f472.camel@mediatek.com> Subject: Re: [PATCH v16 3/8] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: CK Hu To: Bo-Chen Chen , , , , , , , , , , CC: , , , , , , , , , , , , Date: Mon, 8 Aug 2022 13:21:55 +0800 In-Reply-To: <20220805101459.3386-4-rex-bc.chen@mediatek.com> References: <20220805101459.3386-1-rex-bc.chen@mediatek.com> <20220805101459.3386-4-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bo-Chen: On Fri, 2022-08-05 at 18:14 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > Signed-off-by: Bo-Chen Chen > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- [snip] > + > +static void mtk_dp_hpd_sink_event(struct mtk_dp *mtk_dp) > +{ > + ssize_t ret; > + u8 link_status[DP_LINK_STATUS_SIZE] = {}; > + u32 link_status_reg = DP_LANE0_1_STATUS; > + > + ret = drm_dp_dpcd_read(&mtk_dp->aux, link_status_reg, > link_status, > + sizeof(link_status)); > + if (!ret) { > + drm_err(mtk_dp->drm_dev, "Read link status failed\n"); > + return; > + } > + > + if (!drm_dp_channel_eq_ok(link_status, mtk_dp- > >train_info.lane_count)) { > + drm_err(mtk_dp->drm_dev, "Channel EQ failed\n"); > + return; > + } > + > + if (link_status[1] & DP_REMOTE_CONTROL_COMMAND_PENDING) I does not see any other DP driver process DP_REMOTE_CONTROL_COMMAND_PENDING, why mtk dp driver process it? If this is an advanced function, separate this to an independent patch. Regards, CK > + drm_dp_dpcd_writeb(&mtk_dp->aux, > DP_DEVICE_SERVICE_IRQ_VECTOR, > + DP_REMOTE_CONTROL_COMMAND_PENDING); > +} > + >