[PATCH] x86/acpi/cstate delete some unuseful operations

[TimGuo <timguo@zhaoxin.com>]

Unuseful cache flush operations which will be executed by ucode when entering C3 will
cause larger C3 enter latency. And the bus master disable operation is not need for
centaur platforms.

Signed-off-by: TimGuo <timguo@zhaoxin.com>
---
 arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index dde437f..3eee490 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
        if (c->x86_vendor == X86_VENDOR_INTEL &&
            (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
                        flags->bm_control = 0;
+
+       if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+               /*
+                * on all centaur CPUs, sw need not execute cache flush operation
+                * when entering C3 type state.
+                *
+                * On all Centaur platforms, ARB_DISABLE is not required while
+                * entering C3 type state.
+                */
+               flags->bm_check = 1;
+               flags->bm_control = 0;
+        }
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);

--
1.9.1



保密声明：
本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。
CONFIDENTIAL NOTE:
This email contains confidential or legally privileged information and is for the sole use of its intended recipient. Any unauthorized review, use, copying or forwarding of this email or the content of this email is strictly prohibited.