From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752170AbeADC3x (ORCPT + 1 other); Wed, 3 Jan 2018 21:29:53 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:35210 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752116AbeADC3f (ORCPT ); Wed, 3 Jan 2018 21:29:35 -0500 X-Google-Smtp-Source: ACJfBouP2OJlt+JP3Q3XUJTwG7p+hBLtHPB1kYDazYpb743dzFxI6j8UimtkFhIMSaBHyc2JJ39mfA== From: "Ji-Ze Hong (Peter Hong)" X-Google-Original-From: "Ji-Ze Hong (Peter Hong)" To: johan@kernel.org Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, peter_hong@fintek.com.tw, "Ji-Ze Hong (Peter Hong)" Subject: [PATCH V2 5/5] usb: serial: f81534: fix tx error on some baud rate Date: Thu, 4 Jan 2018 10:29:21 +0800 Message-Id: <1515032961-29131-5-git-send-email-hpeter+linux_kernel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515032961-29131-1-git-send-email-hpeter+linux_kernel@gmail.com> References: <1515032961-29131-1-git-send-email-hpeter+linux_kernel@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The F81532/534 had 4 clocksource 1.846/18.46/14.77/24MHz and baud rates can be up to 1.5Mbits with 24MHz. But on some baud rate (384~500kps), the TX side will send the data frame too close to treat frame error on RX side. This patch will force all TX data frame with delay 1bit gap. Signed-off-by: Ji-Ze Hong (Peter Hong) --- V2: 1: First introduced in this series patches. drivers/usb/serial/f81534.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/serial/f81534.c b/drivers/usb/serial/f81534.c index a4666171239a..513805eeae6a 100644 --- a/drivers/usb/serial/f81534.c +++ b/drivers/usb/serial/f81534.c @@ -130,6 +130,7 @@ #define F81534_CLK_18_46_MHZ (F81534_UART_EN | BIT(1)) #define F81534_CLK_24_MHZ (F81534_UART_EN | BIT(2)) #define F81534_CLK_14_77_MHZ (F81534_UART_EN | BIT(1) | BIT(2)) +#define F81534_CLK_TX_DELAY_1BIT BIT(3) #define F81534_CLK_RS485_MODE BIT(4) #define F81534_CLK_RS485_INVERT BIT(5) @@ -1438,6 +1439,11 @@ static int f81534_port_probe(struct usb_serial_port *port) break; } + /* + * We'll make tx frame error when baud rate from 384~500kps. So we'll + * delay all tx data frame with 1bit. + */ + port_priv->shadow_clk |= F81534_CLK_TX_DELAY_1BIT; return f81534_set_port_output_pin(port); } -- 2.7.4