From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226UkoDU49lnopaerPYXvyK4Ofg7+cFV+0Xd2uckgAKy5pL1TRvMSFFZjw4kjAbAQ2p7ZihA ARC-Seal: i=1; a=rsa-sha256; t=1516476491; cv=none; d=google.com; s=arc-20160816; b=E1Q381oaW+RIWObp0Nqhew/klf3lK5uW+wIiDCiE6vizusznAiMSEbequTwV+Z4V2u YaULA/rrK3Z9x1y5lcLGzDzgYhZ0o4EfxDJj2vmOU3uRWvkRCJMng8RGEUi4CyrgNKrE mUAQ8zFAsTslyoEIAff/xgO4Mq7qfB372tbg38Y7uLtBmYt9MNP/K9q6smmsKzZSA8A/ luLjCpLn+niEEm3tQG0C7y5b7bgvL18SwiTAH7+xBzmDeTxf1Mip/TxaLOUJNVNlPAZP UThWGNRy5Mgl01C+5qf1LRP53N+degs8rtnYfGIiLgtgBDnwxbEW7ABLGi6QJRUuNG9U 2EUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=cB+0f/8nQbtTpjmarM0FY5BRIuj/RLKxFSRKr//dBls=; b=hwanmKH+Ta+XG+CyxfjxLVSSnMCXC/cqO5LJzYYukBuI1xqkAhcdPWXXtZ8lEc43Fa JOMTLa7d7/hZW/fsuJ9vvCHIQrHybM5qHo+gs3mQglkQVbHeSwyBMo/intrB+dYl9gL6 wfYPg/104QPlyqF9PYFuXgrLHTr0FFq5SeobmtqP6y5Lq92QeGUI2n5NEit5G993DTeO raUzFQCwJV2CoLepO2QGZ5m3xi4AtpjIg8Yd+QE4XQzvGXLtM5B1zfwsumunltZfAlhd JIwH7X8cL6gHQTnWotRJ1+xYc7e5g70PF2H5oV5CsiYEAC4UWhrkpLBG2YPr3y4Ztw8U C8Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.de header.s=amazon201209 header.b=QMaGna+A; spf=pass (google.com: domain of prvs=551b82ed1=karahmed@amazon.com designates 207.171.184.25 as permitted sender) smtp.mailfrom=prvs=551b82ed1=karahmed@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.de Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.de header.s=amazon201209 header.b=QMaGna+A; spf=pass (google.com: domain of prvs=551b82ed1=karahmed@amazon.com designates 207.171.184.25 as permitted sender) smtp.mailfrom=prvs=551b82ed1=karahmed@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.de X-IronPort-AV: E=Sophos;i="5.46,387,1511827200"; d="scan'208";a="720491807" From: KarimAllah Ahmed To: linux-kernel@vger.kernel.org Cc: KarimAllah Ahmed , Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Arjan van de Ven , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , David Woodhouse , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Linus Torvalds , Masami Hiramatsu , Paolo Bonzini , Peter Zijlstra , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Thomas Gleixner , Tim Chen , Tom Lendacky , kvm@vger.kernel.org, x86@kernel.org, Arjan Van De Ven Subject: [RFC 02/10] x86/kvm: Add IBPB support Date: Sat, 20 Jan 2018 20:22:53 +0100 Message-Id: <1516476182-5153-3-git-send-email-karahmed@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516476182-5153-1-git-send-email-karahmed@amazon.de> References: <1516476182-5153-1-git-send-email-karahmed@amazon.de> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590140854319668617?= X-GMAIL-MSGID: =?utf-8?q?1590140854319668617?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Ashok Raj Add MSR passthrough for MSR_IA32_PRED_CMD and place branch predictor barriers on switching between VMs to avoid inter VM specte-v2 attacks. [peterz: rebase and changelog rewrite] [dwmw2: fixes] [karahmed: - vmx: expose PRED_CMD whenever it is available - svm: only pass through IBPB if it is available] Cc: Asit Mallick Cc: Dave Hansen Cc: Arjan Van De Ven Cc: Tim Chen Cc: Linus Torvalds Cc: Andrea Arcangeli Cc: Andi Kleen Cc: Thomas Gleixner Cc: Dan Williams Cc: Jun Nakajima Cc: Andy Lutomirski Cc: Greg KH Cc: David Woodhouse Cc: Paolo Bonzini Signed-off-by: Ashok Raj Signed-off-by: Peter Zijlstra (Intel) Link: http://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok.raj@intel.com Signed-off-by: David Woodhouse Signed-off-by: KarimAllah Ahmed --- arch/x86/kvm/svm.c | 14 ++++++++++++++ arch/x86/kvm/vmx.c | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 2744b973..cfdb9ab 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -529,6 +529,7 @@ struct svm_cpu_data { struct kvm_ldttss_desc *tss_desc; struct page *save_area; + struct vmcb *current_vmcb; }; static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); @@ -918,6 +919,9 @@ static void svm_vcpu_init_msrpm(u32 *msrpm) set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); } + + if (boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) + set_msr_interception(msrpm, MSR_IA32_PRED_CMD, 1, 1); } static void add_msr_offset(u32 offset) @@ -1706,11 +1710,17 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu) __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); kvm_vcpu_uninit(vcpu); kmem_cache_free(kvm_vcpu_cache, svm); + /* + * The vmcb page can be recycled, causing a false negative in + * svm_vcpu_load(). So do a full IBPB now. + */ + indirect_branch_prediction_barrier(); } static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { struct vcpu_svm *svm = to_svm(vcpu); + struct svm_cpu_data *sd = per_cpu(svm_data, cpu); int i; if (unlikely(cpu != vcpu->cpu)) { @@ -1739,6 +1749,10 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (static_cpu_has(X86_FEATURE_RDTSCP)) wrmsrl(MSR_TSC_AUX, svm->tsc_aux); + if (sd->current_vmcb != svm->vmcb) { + sd->current_vmcb = svm->vmcb; + indirect_branch_prediction_barrier(); + } avic_vcpu_load(vcpu, cpu); } diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index d1e25db..3b64de2 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2279,6 +2279,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; vmcs_load(vmx->loaded_vmcs->vmcs); + indirect_branch_prediction_barrier(); } if (!already_loaded) { @@ -6791,6 +6792,9 @@ static __init int hardware_setup(void) kvm_tsc_scaling_ratio_frac_bits = 48; } + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) + vmx_disable_intercept_for_msr(MSR_IA32_PRED_CMD, false); + vmx_disable_intercept_for_msr(MSR_FS_BASE, false); vmx_disable_intercept_for_msr(MSR_GS_BASE, false); vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); -- 2.7.4