From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751392AbeAWAcS (ORCPT ); Mon, 22 Jan 2018 19:32:18 -0500 Received: from mga06.intel.com ([134.134.136.31]:28079 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751293AbeAWAcR (ORCPT ); Mon, 22 Jan 2018 19:32:17 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,398,1511856000"; d="scan'208";a="12382151" From: "Mehta, Sohil" To: "tglx@linutronix.de" , "hpa@zytor.com" , "andriy.shevchenko@linux.intel.com" , "mingo@redhat.com" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" CC: "mitake@dcl.info.waseda.ac.jp" Subject: Re: [PATCH v1] x86/io: Define readq()/writeq() to use 64-bit type Thread-Topic: [PATCH v1] x86/io: Define readq()/writeq() to use 64-bit type Thread-Index: AQHTkTJ4WfY95fdVfkqnEy/XJR2WMaOBJyYA Date: Tue, 23 Jan 2018 00:32:14 +0000 Message-ID: <1516667578.153063.78.camel@intel.com> References: <20180119143322.16555-1-andriy.shevchenko@linux.intel.com> In-Reply-To: <20180119143322.16555-1-andriy.shevchenko@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.25.110.4] Content-Type: text/plain; charset="utf-8" Content-ID: <205265F487567741BF5284FE2EA0B4AA@intel.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w0N0WMQ5004238 On Fri, 2018-01-19 at 16:33 +0200, Andy Shevchenko wrote: > Since non atomic readq() and writeq() were added some of the drivers > would like to use it in a manner of: > >  #include > ... >  pr_debug("Debug value of some register: %016llx\n", readq(addr)); > > However, lo_hi_readq() always returns __u64 data, while readq() > on x86_64 defines it as unsigned long. and thus compiler warns > about type mismatch, although they are both 64-bit on x86_64. > > Convert readq() and writeq() on x86 to operate on deterministic > 64-bit type. The most of architectures in the kernel already are > using > either unsigned long long, or u64 type for readq() / writeq(). > This change propagates consistency in that sense. > > While this is not an issue per se, though if someone wants to address > it, > the anchor could be the commit > >   797a796a13df ("asm-generic: architecture independent readq/writeq > for 32bit environment") > > where non-atomic variants had been introduced. > > Note, there are only few users of above pattern and they will not be > affected because they do cast returned value. The actual warning has > been issued on not-yet-upstreamed code. > > Potentially we might get a new warnings if some 64-bit only code > assigns returned value to unsigned long type of variable. This is > assumed to be addressed on case-by-case basis. > > Reported-by: lkp > Cc: Hitoshi Mitake > Cc: "Mehta, Sohil" > Signed-off-by: Andy Shevchenko > --- >  arch/x86/include/asm/io.h | 8 ++++---- >  1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h > index 95e948627fd0..365f5ba9222b 100644 > --- a/arch/x86/include/asm/io.h > +++ b/arch/x86/include/asm/io.h > @@ -94,10 +94,10 @@ build_mmio_write(__writel, "l", unsigned int, > "r", ) >   >  #ifdef CONFIG_X86_64 >   > -build_mmio_read(readq, "q", unsigned long, "=r", :"memory") > -build_mmio_read(__readq, "q", unsigned long, "=r", ) > -build_mmio_write(writeq, "q", unsigned long, "r", :"memory") > -build_mmio_write(__writeq, "q", unsigned long, "r", ) > +build_mmio_read(readq, "q", unsigned long long, "=r", :"memory") > +build_mmio_read(__readq, "q", unsigned long long, "=r", ) > +build_mmio_write(writeq, "q", unsigned long long, "r", :"memory") > +build_mmio_write(__writeq, "q", unsigned long long, "r", ) >   >  #define readq_relaxed(a) __readq(a) >  #define writeq_relaxed(v, a) __writeq(v, a) The patch works for me: Tested-by: Sohil Mehta Sohil