From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224bkrcvJ5/rAhI9/Ug2bbjWFHZw4SqueKiJPy6AweumPciIy9DH8/eFrQRu9PB4P2DWkG8s ARC-Seal: i=1; a=rsa-sha256; t=1516726399; cv=none; d=google.com; s=arc-20160816; b=miIoShWGZbQSEBzU0bTZJjmusruWLWbb7fDpUVCcrTklTCAYVSOm3PY5gYfPIIh2Jy N+3dSMIhXQ/hUuZ86KvKRDQi3qvjXmH0VVCWRr2fArSeHxEFwSoZgebZxzzSxd6NyflA o5s6p8aJo04xv9MVCAksPJsxNaz4C09yQQC2PDUw7QciZvOyz9kiB3LI2REH1Z/H1398 mYZn5W3Kbrw6da0cbpggckJJFPpbnaaPYZBzZThZO6kXOeWgzyUPG/piQqra1FubpEZ6 /hlSVWXF/ApU+1c1G/wL34MACQGrtujtxXfZUgtvl49ZKMDX8465N08ftPc5qMniYXRF CbzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=lja7L+pBu9UtXAxAG7s4nLD4n0vmu02OzwKlBzESVO0=; b=PD0WNPcBHfbD+GvROvIHfgufQhM4dgdOfRgSwor1wzd4BPCMXkU4cj+RtOcTXe0dBs tBwu+cG/jxqRaaIn31FQmJUH7QTbMdELPsRWUw+cg7vbihXouhuvd48DPRy2LJudgLT+ GhhGzBpdr6RQK2gYRNiuJ4j2b56AChe8+W77NtX1zjRMss+nNls//blbkwWFmTC+UdvR JCWx/67MiDGofKk1WWxk5tToW+R2qcUEV4RpBM8rHyPU0W6oFpsK2Tm/ne+zp6XtGayz Rq03mfinmfecnlNDGiB1LUevIgRNrXgKKgOUj7ZM0l3HKpdxOspJazG+vvoLQwqFaWAE /c9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=SX0PFbNo; spf=pass (google.com: domain of prvs=5540fad8f=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=5540fad8f=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=SX0PFbNo; spf=pass (google.com: domain of prvs=5540fad8f=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=5540fad8f=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,402,1511827200"; d="scan'208";a="589159640" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, thomas.lendacky@amd.com Subject: [PATCH v2 2/5] x86/cpufeatures: Add Intel feature bits for Speculation Control Date: Tue, 23 Jan 2018 16:52:52 +0000 Message-Id: <1516726375-25168-3-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516726375-25168-1-git-send-email-dwmw@amazon.co.uk> References: <1516726375-25168-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590402900695283949?= X-GMAIL-MSGID: =?utf-8?q?1590402900695283949?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add three feature bits exposed by new microcode on Intel CPUs for speculation control. Signed-off-by: David Woodhouse Reviewed-by: Borislav Petkov --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7b25cf3..0a51070 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -320,6 +320,9 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation Control (IBRS + IBPB) */ +#define X86_FEATURE_STIBP (18*32+27) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ /* * BUG word(s) -- 2.7.4