From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965000AbeAXRmJ (ORCPT ); Wed, 24 Jan 2018 12:42:09 -0500 Received: from twosheds.infradead.org ([90.155.92.209]:47952 "EHLO twosheds.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964850AbeAXRmI (ORCPT ); Wed, 24 Jan 2018 12:42:08 -0500 Message-ID: <1516815723.13558.164.camel@infradead.org> Subject: Re: [PATCH v2 5/5] x86/pti: Do not enable PTI on fixed Intel processors From: David Woodhouse To: Alan Cox Cc: Dave Hansen , linux-kernel@vger.kernel.org In-Reply-To: <20180124170652.4c78ca17@alans-desktop> References: <1516726375-25168-1-git-send-email-dwmw@amazon.co.uk> <1516726375-25168-6-git-send-email-dwmw@amazon.co.uk> <20180123173312.1d8cf02f@alans-desktop> <1516811127.13558.150.camel@infradead.org> <20180124170652.4c78ca17@alans-desktop> Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAG1BMVEUHBwcUFBQpKSlGRkZhYWF9fX2Xl5eysrLMzMxFF+rXAAACaElEQVQ4y21UQXbbIBQE9wJALmAg6ToWON22FrhZthHgbvssUPathC7QWMful2JHSmtWwGg+zPxBCE0DU4QoJQgRgsg4w2gJjBNE8PjFBZgnQMBs+uZ1NQNQjZO3BV4AGDFC0f+l4DBG0VUAM4yv7SO8IgRdHXQ+A78HKL5OAeCfNQV5cHX8DsBUyIJKtYbt98BKaGNCKjfgFVkqYVLbkHKsRsbSCSa0T6npIqLrpRBgQKHUpQmgs9eEKaiUcooE8WWfCGVnBiUcn1uF2XhbfmN9apKnmMP2K4kizKkQWxuaVNOpU2cACIyxO1Po8ETHcXEDMVnozcejkAYA9iaD4pU0ZvNQ8VurNnTuFAYVtuIPUZW25PjDIjQAlGyffIiRQxoWAZBmJ0LTdW2Nyc0iP3DqRhxizvGJkBWZmyFVyZkddWzmBoIBVMpCCJ1CFzl98xav4VJKSSD45KbUT75ixikTphDSRh8+Uz7JLgUTAgAFwzqzjxc/nDY7WUApqY0OMdTwCKZSXplSKkgIRCHElCp8ZnhnKqXuwcNbk1L0VXE+I9alUXoHlLHl3mv7/dWQlJwtjREC7mu9L/U2jQyMUuO2EDS4q9Kl2ddm232bxIE5pjJuVwiljNn/Cfv25/T0cu5cZbwHGVq7h/zp0B4n3S99V/utD+Uo8BiGx9xCsOAV5z7/tjo4Z4z1Lvb90KZ7eFOoOeXOukqF2seo234YYuaQPpRP+cVZU5adT1Edun5Iz3z8fTz3+eSDh0Ip1c7zx1MaijGzTd/3MbRuBHz8cvcVgCMBRpOHvgu59WDhoat+nIZm+LWm9C/aaaGq5DCP9QAAAABJRU5ErkJggg== Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-PF8qvMYuvNqfhEQYzsrL" Date: Wed, 24 Jan 2018 17:42:03 +0000 Mime-Version: 1.0 X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 X-SRS-Rewrite: SMTP reverse-path rewritten from by twosheds.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-PF8qvMYuvNqfhEQYzsrL Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2018-01-24 at 17:07 +0000, Alan Cox wrote: > >=20 > > =C2=A0 > > +static const __initdata struct x86_cpu_id cpu_no_meltdown[] =3D { > > + { X86_VENDOR_AMD }, > > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, > > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, > > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, > > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, > > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, > As Linus said this should be no_specualtion[] >=20 > If we are going to capture 32bit here with your lines below I'll send you > an update at some point with all the 32bit families hunted down (some > like the CE4100 may take a bit of hunting) >=20 >=20 > >=20 > > + { X86_VENDOR_ANY, 5 }, > AND K5 speculates, Cyrix 6x86 speculates, IDT WinChip does not. I think > this should be >=20 > X86_VENDOR_ANY, 4 > X86_VENDOR_INTEL, 5, > X86_VENDOR_CENTAUR, 5, Hm, for the specific case of controlling X86_BUG_CPU_MELTDOWN it's not just "speculates" which is the criterion. It's "optimises away the permissions checks while speculating, on the assumption that it'll be fixed up before retiring the instruction". I think X86_BUG_CPU_SPECTRE_V2 might end being a lot closer to just "it speculates". > >=20 > > +static bool __init early_cpu_vulnerable_meltdown(struct cpuinfo_x86 *c= ) > > +{ > > + u64 ia32_cap =3D 0; > > + > > + if (x86_match_cpu(cpu_no_meltdown)) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0return false; > These processors are also not vulnerable to spectre, so this patch > doesn't set the other flags correctly - that's why we need two levels of > logic here. "Bonnell" and "Saltwell" uarch Atom processors are not > vulnerable to Meltdown or Spectre, neithr is a 486, Pentium, Quark etc. Yeah, I've deliberately not touched Spectre for this case. By the time the dust settles we might end up with a bunch of different match tables, *one* of which is "does not speculate at all". And the conditions for the different bugs will each use different sets of match tables. For example =C2=A0if (!x86_match_cpu(cpu_no_speculation_at_all) && =C2=A0 =C2=A0 =C2=A0!x86_match_cpu(speculation_but_no_meltdown) && =C2=A0 =C2=A0 =C2=A0!cpu_sets_rdcl_no()) setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); =C2=A0if (!x86_match_cpu(cpu_no_speculation_at_all) && =C2=A0 =C2=A0 =C2=A0!x86_match_cpu(no_branch_target_buffer)) setup_force_cpu_bug(X86_BUG_SPECTRE_V2); ... Let's gather the data and see how we want to break it down according to which subsets are common. In the mean time Meltdown is the big one which has performance implications and wants to be avoided if we can. --=-PF8qvMYuvNqfhEQYzsrL Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCEFQw ggUxMIIEGaADAgECAhBNRhEyk/HZ7naOeTHWrzuAMA0GCSqGSIb3DQEBCwUAMIGXMQswCQYDVQQG EwJHQjEbMBkGA1UECBMSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHEwdTYWxmb3JkMRowGAYD VQQKExFDT01PRE8gQ0EgTGltaXRlZDE9MDsGA1UEAxM0Q09NT0RPIFJTQSBDbGllbnQgQXV0aGVu dGljYXRpb24gYW5kIFNlY3VyZSBFbWFpbCBDQTAeFw0xNzEyMjEwMDAwMDBaFw0xODEyMjEyMzU5 NTlaMCQxIjAgBgkqhkiG9w0BCQEWE2R3bXcyQGluZnJhZGVhZC5vcmcwggEiMA0GCSqGSIb3DQEB AQUAA4IBDwAwggEKAoIBAQDgzLNWa18DNpGUj/ZeH0Sgz53ESIbzdPw3OJeuNP6jZhxZojbyfxbM hETscxI/Hj6UZ4a7sHm5BkVjlsB1Af2Za/PXUt8MmLAcPMHkMPGunvkUibEvblDvpqMkQZlaZM+t 5PqFmWkbehLaEvbpNY7dmEAAeKh4klTzJzrr5AAzaCQ32cA2e3+DEIv5O5l9ViMIjy/JM+xMQrfX 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