From: Wu Hao <hao.wu@intel.com>
To: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: linux-api@vger.kernel.org, luwei.kang@intel.com,
yi.z.zhang@intel.com, hao.wu@intel.com,
Tim Whisonant <tim.whisonant@intel.com>,
Enno Luebbers <enno.luebbers@intel.com>,
Shiva Rao <shiva.rao@intel.com>,
Christopher Rauer <christopher.rauer@intel.com>,
Xiao Guangrong <guangrong.xiao@linux.intel.com>
Subject: [PATCH v4 16/24] fpga: dfl: add fpga manager platform driver for FME
Date: Tue, 13 Feb 2018 17:24:45 +0800 [thread overview]
Message-ID: <1518513893-4719-17-git-send-email-hao.wu@intel.com> (raw)
In-Reply-To: <1518513893-4719-1-git-send-email-hao.wu@intel.com>
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.
Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Kang Luwei <luwei.kang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
---
v3: rename driver to dfl-fpga-fme-mgr
implemented status callback for fpga manager
rebased due to fpga api changes
v4: rename to dfl-fme-mgr, and fix SPDX license issue
add pr_credit comments and improve dev_err message
remove interface_id sysfs interface
include dfl-fme-pr.h instead of dfl.h
---
drivers/fpga/Kconfig | 6 +
drivers/fpga/Makefile | 1 +
drivers/fpga/dfl-fme-mgr.c | 290 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 297 insertions(+)
create mode 100644 drivers/fpga/dfl-fme-mgr.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 103d5e2..89f76e8 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -150,6 +150,12 @@ config FPGA_DFL_FME
FPGA platform level management features. There shall be 1 FME
per DFL based FPGA device.
+config FPGA_DFL_FME_MGR
+ tristate "FPGA DFL FME Manager Driver"
+ depends on FPGA_DFL_FME
+ help
+ Say Y to enable FPGA Manager driver for FPGA Management Engine.
+
config FPGA_DFL_PCI
tristate "FPGA Device Feature List (DFL) PCIe Device Driver"
depends on PCI && FPGA_DFL
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 3c44fc9..f82814a 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
# FPGA Device Feature List Support
obj-$(CONFIG_FPGA_DFL) += dfl.o
obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
+obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
new file mode 100644
index 0000000..2f92c29
--- /dev/null
+++ b/drivers/fpga/dfl-fme-mgr.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * FPGA Manager Driver for FPGA Management Engine (FME)
+ *
+ * Copyright (C) 2017 Intel Corporation, Inc.
+ *
+ * Authors:
+ * Kang Luwei <luwei.kang@intel.com>
+ * Xiao Guangrong <guangrong.xiao@linux.intel.com>
+ * Wu Hao <hao.wu@intel.com>
+ * Joseph Grecco <joe.grecco@intel.com>
+ * Enno Luebbers <enno.luebbers@intel.com>
+ * Tim Whisonant <tim.whisonant@intel.com>
+ * Ananda Ravuri <ananda.ravuri@intel.com>
+ * Christopher Rauer <christopher.rauer@intel.com>
+ * Henry Mitchel <henry.mitchel@intel.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#include "dfl-fme-pr.h"
+
+#define PR_WAIT_TIMEOUT 8000000
+#define PR_HOST_STATUS_IDLE 0
+
+struct fme_mgr_priv {
+ void __iomem *ioaddr;
+ u64 pr_error;
+};
+
+static u64 pr_error_to_mgr_status(u64 err)
+{
+ u64 status = 0;
+
+ if (err & FME_PR_ERR_OPERATION_ERR)
+ status |= FPGA_MGR_STATUS_OPERATION_ERR;
+ if (err & FME_PR_ERR_CRC_ERR)
+ status |= FPGA_MGR_STATUS_CRC_ERR;
+ if (err & FME_PR_ERR_INCOMPATIBLE_BS)
+ status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
+ if (err & FME_PR_ERR_PROTOCOL_ERR)
+ status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
+ if (err & FME_PR_ERR_FIFO_OVERFLOW)
+ status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
+
+ return status;
+}
+
+static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
+{
+ u64 pr_status, pr_error;
+
+ pr_status = readq(fme_pr + FME_PR_STS);
+ if (!(pr_status & FME_PR_STS_PR_STS))
+ return 0;
+
+ pr_error = readq(fme_pr + FME_PR_ERR);
+ writeq(pr_error, fme_pr + FME_PR_ERR);
+
+ return pr_error;
+}
+
+static int fme_mgr_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ struct device *dev = &mgr->dev;
+ struct fme_mgr_priv *priv = mgr->priv;
+ void __iomem *fme_pr = priv->ioaddr;
+ u64 pr_ctrl, pr_status;
+
+ if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+ dev_err(dev, "only supports partial reconfiguration.\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "resetting PR before initiated PR\n");
+
+ pr_ctrl = readq(fme_pr + FME_PR_CTRL);
+ pr_ctrl |= FME_PR_CTRL_PR_RST;
+ writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
+
+ if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
+ pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
+ PR_WAIT_TIMEOUT)) {
+ dev_err(dev, "PR Reset ACK timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ pr_ctrl = readq(fme_pr + FME_PR_CTRL);
+ pr_ctrl &= ~FME_PR_CTRL_PR_RST;
+ writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
+
+ dev_dbg(dev,
+ "waiting for PR resource in HW to be initialized and ready\n");
+
+ if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
+ (pr_status & FME_PR_STS_PR_STS) ==
+ FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
+ dev_err(dev, "PR Status timeout\n");
+ priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(dev, "check and clear previous PR error\n");
+ priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
+ if (priv->pr_error)
+ dev_dbg(dev, "previous PR error detected %llx\n",
+ (unsigned long long)priv->pr_error);
+
+ dev_dbg(dev, "set PR port ID\n");
+
+ pr_ctrl = readq(fme_pr + FME_PR_CTRL);
+ pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
+ pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
+ writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
+
+ return 0;
+}
+
+static int fme_mgr_write(struct fpga_manager *mgr,
+ const char *buf, size_t count)
+{
+ struct device *dev = &mgr->dev;
+ struct fme_mgr_priv *priv = mgr->priv;
+ void __iomem *fme_pr = priv->ioaddr;
+ u64 pr_ctrl, pr_status, pr_data;
+ int delay = 0, pr_credit, i = 0;
+
+ dev_dbg(dev, "start request\n");
+
+ pr_ctrl = readq(fme_pr + FME_PR_CTRL);
+ pr_ctrl |= FME_PR_CTRL_PR_START;
+ writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
+
+ dev_dbg(dev, "pushing data from bitstream to HW\n");
+
+ /*
+ * driver can push data to PR hardware using PR_DATA register once HW
+ * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
+ * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
+ * to wait for enough pr_credit from hardware by polling.
+ */
+ pr_status = readq(fme_pr + FME_PR_STS);
+ pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
+
+ while (count > 0) {
+ while (pr_credit <= 1) {
+ if (delay++ > PR_WAIT_TIMEOUT) {
+ dev_err(dev, "PR_CREDIT timeout\n");
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+
+ pr_status = readq(fme_pr + FME_PR_STS);
+ pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
+ }
+
+ if (count >= 4) {
+ pr_data = 0;
+ pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
+ *(((u32 *)buf) + i));
+ writeq(pr_data, fme_pr + FME_PR_DATA);
+ count -= 4;
+ pr_credit--;
+ i++;
+ } else {
+ WARN_ON(1);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int fme_mgr_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ struct device *dev = &mgr->dev;
+ struct fme_mgr_priv *priv = mgr->priv;
+ void __iomem *fme_pr = priv->ioaddr;
+ u64 pr_ctrl;
+
+ pr_ctrl = readq(fme_pr + FME_PR_CTRL);
+ pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
+ writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
+
+ dev_dbg(dev, "green bitstream push complete\n");
+ dev_dbg(dev, "waiting for HW to release PR resource\n");
+
+ if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
+ !(pr_ctrl & FME_PR_CTRL_PR_START), 1,
+ PR_WAIT_TIMEOUT)) {
+ dev_err(dev, "PR Completion ACK timeout.\n");
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(dev, "PR operation complete, checking status\n");
+ priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
+ if (priv->pr_error) {
+ dev_dbg(dev, "PR error detected %llx\n",
+ (unsigned long long)priv->pr_error);
+ return -EIO;
+ }
+
+ dev_dbg(dev, "PR done successfully\n");
+
+ return 0;
+}
+
+static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static u64 fme_mgr_status(struct fpga_manager *mgr)
+{
+ struct fme_mgr_priv *priv = mgr->priv;
+
+ return pr_error_to_mgr_status(priv->pr_error);
+}
+
+static const struct fpga_manager_ops fme_mgr_ops = {
+ .write_init = fme_mgr_write_init,
+ .write = fme_mgr_write,
+ .write_complete = fme_mgr_write_complete,
+ .state = fme_mgr_state,
+ .status = fme_mgr_status,
+};
+
+static int fme_mgr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct fme_mgr_priv *priv;
+ struct fpga_manager *mgr;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->ioaddr = devm_ioremap(dev, res->start, resource_size(res));
+ if (IS_ERR(priv->ioaddr))
+ return PTR_ERR(priv->ioaddr);
+
+ mgr = devm_kzalloc(dev, sizeof(*mgr), GFP_KERNEL);
+ if (!mgr)
+ return -ENOMEM;
+
+ mgr->name = "DFL FPGA Manager";
+ mgr->mops = &fme_mgr_ops;
+ mgr->priv = priv;
+ mgr->parent = dev;
+ platform_set_drvdata(pdev, mgr);
+
+ ret = fpga_mgr_register(mgr);
+ if (ret)
+ dev_err(dev, "unable to register FPGA manager\n");
+
+ return ret;
+}
+
+static int fme_mgr_remove(struct platform_device *pdev)
+{
+ struct fpga_manager *mgr = platform_get_drvdata(pdev);
+
+ fpga_mgr_unregister(mgr);
+
+ return 0;
+}
+
+static struct platform_driver fme_mgr_driver = {
+ .driver = {
+ .name = FPGA_DFL_FME_MGR,
+ },
+ .probe = fme_mgr_probe,
+ .remove = fme_mgr_remove,
+};
+
+module_platform_driver(fme_mgr_driver);
+
+MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:dfl-fme-mgr");
--
2.7.4
next prev parent reply other threads:[~2018-02-13 9:35 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-13 9:24 [PATCH v4 00/24] FPGA Device Feature List (DFL) Device Drivers Wu Hao
2018-02-13 9:24 ` [PATCH v4 01/24] docs: fpga: add a document for FPGA Device Feature List (DFL) Framework Overview Wu Hao
2018-02-26 22:48 ` Alan Tull
2018-02-27 2:12 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 02/24] fpga: mgr: add region_id to fpga_image_info Wu Hao
2018-02-13 9:24 ` [PATCH v4 03/24] fpga: mgr: add status for fpga-manager Wu Hao
2018-02-14 15:55 ` Alan Tull
2018-02-15 9:42 ` Wu, Hao
2018-02-14 20:55 ` Moritz Fischer
2018-02-13 9:24 ` [PATCH v4 04/24] fpga: add device feature list support Wu Hao
2018-03-21 23:54 ` Alan Tull
2018-03-22 4:40 ` Wu Hao
2018-03-22 21:31 ` Alan Tull
2018-03-23 4:33 ` Wu Hao
2018-03-26 17:21 ` Alan Tull
2018-03-27 2:35 ` Wu Hao
2018-03-29 21:57 ` Alan Tull
2018-04-02 4:22 ` Wu Hao
2018-04-02 19:06 ` Alan Tull
2018-04-03 1:36 ` Wu Hao
2018-04-04 20:06 ` Alan Tull
2018-04-06 11:01 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 05/24] fpga: dfl: add chardev support for feature devices Wu Hao
2018-02-13 9:24 ` [PATCH v4 06/24] fpga: dfl: adds fpga_cdev_find_port Wu Hao
2018-02-14 16:24 ` Alan Tull
2018-02-15 9:46 ` Wu, Hao
2018-02-14 20:55 ` Moritz Fischer
2018-02-13 9:24 ` [PATCH v4 07/24] fpga: dfl: add feature device infrastructure Wu Hao
2018-02-14 21:03 ` Moritz Fischer
2018-02-14 21:13 ` Alan Tull
2018-02-15 10:05 ` Wu, Hao
2018-02-15 19:49 ` Moritz Fischer
2018-02-18 2:15 ` Wu, Hao
2018-02-13 9:24 ` [PATCH v4 08/24] fpga: add FPGA DFL PCIe device driver Wu Hao
2018-03-13 16:05 ` Alan Tull
2018-03-15 18:49 ` Moritz Fischer
2018-03-16 4:29 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 09/24] fpga: dfl-pci: add enumeration for feature devices Wu Hao
2018-03-13 18:30 ` Alan Tull
2018-03-14 5:21 ` Wu Hao
2018-03-14 14:48 ` Alan Tull
2018-02-13 9:24 ` [PATCH v4 10/24] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao
2018-04-05 18:35 ` Alan Tull
2018-04-06 11:04 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 11/24] fpga: dfl: fme: add header sub feature support Wu Hao
2018-02-14 16:36 ` Alan Tull
2018-02-13 9:24 ` [PATCH v4 12/24] fpga: dfl: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-03-19 18:29 ` Alan Tull
2018-03-20 6:46 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 13/24] fpga: region: add compat_id support Wu Hao
2018-02-28 22:55 ` Alan Tull
2018-03-01 6:17 ` Wu Hao
2018-03-05 19:42 ` Alan Tull
2018-03-06 0:56 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 14/24] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao
2018-03-05 22:46 ` Alan Tull
2018-03-06 2:08 ` Wu Hao
2018-03-06 18:29 ` Alan Tull
2018-03-07 4:39 ` Wu Hao
2018-03-11 20:09 ` matthew.gerlach
2018-03-12 4:29 ` Wu Hao
2018-03-12 18:53 ` Alan Tull
2018-03-12 21:36 ` matthew.gerlach
2018-03-13 1:07 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 15/24] fpga: dfl-fme-pr: add compat_id support for dfl-fme-region platform device Wu Hao
2018-02-28 23:06 ` Alan Tull
2018-03-01 5:49 ` Wu Hao
2018-03-01 15:59 ` Alan Tull
2018-03-01 15:55 ` Wu Hao
2018-02-13 9:24 ` Wu Hao [this message]
2018-03-20 20:32 ` [PATCH v4 16/24] fpga: dfl: add fpga manager platform driver for FME Alan Tull
2018-03-21 2:50 ` Wu Hao
2018-03-21 16:55 ` Moritz Fischer
2018-03-22 6:07 ` Wu Hao
2018-04-05 18:45 ` Alan Tull
2018-04-06 11:11 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 17/24] fpga: dfl: add fpga bridge " Wu Hao
2018-02-13 9:24 ` [PATCH v4 18/24] fpga: dfl: add fpga region " Wu Hao
2018-02-13 9:24 ` [PATCH v4 19/24] fpga: dfl-fme-region: add compat_id support Wu Hao
2018-02-13 9:24 ` [PATCH v4 20/24] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao
2018-03-19 18:40 ` Alan Tull
2018-04-05 18:26 ` Alan Tull
2018-04-06 11:05 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 21/24] fpga: dfl: afu: add header sub feature support Wu Hao
2018-02-13 9:24 ` [PATCH v4 22/24] fpga: dfl: afu: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-02-13 9:24 ` [PATCH v4 23/24] fpga: dfl: afu: add user afu sub feature support Wu Hao
2018-03-19 20:10 ` Alan Tull
2018-03-20 7:10 ` Wu Hao
2018-03-20 18:17 ` Alan Tull
2018-03-21 3:00 ` Wu Hao
2018-03-21 23:50 ` Alan Tull
2018-03-22 4:41 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 24/24] fpga: dfl: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
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