From: John Garry <john.garry@huawei.com>
To: <jolsa@redhat.com>, <ak@linux.intel.com>, <peterz@infradead.org>,
<mingo@redhat.com>, <acme@kernel.org>,
<alexander.shishkin@linux.intel.com>, <namhyung@kernel.org>,
<wcohen@redhat.com>, <will.deacon@arm.com>,
<ganapatrao.kulkarni@cavium.com>
Cc: <linuxarm@huawei.com>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<zhangshaokun@hisilicon.com>,
"John Garry" <john.garry@huawei.com>
Subject: [PATCH v2 05/11] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
Date: Sat, 24 Feb 2018 00:05:26 +0800 [thread overview]
Message-ID: <1519401932-205051-6-git-send-email-john.garry@huawei.com> (raw)
In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com>
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 ----------------------
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 ++++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
3 files changed, 63 insertions(+), 63 deletions(-)
delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
deleted file mode 100644
index 2db45c4..0000000
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
+++ /dev/null
@@ -1,62 +0,0 @@
-[
- {
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
- },
- {
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
- },
- {
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
- },
- {
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
- },
- {
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
- },
- {
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
- },
- {
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
new file mode 100644
index 0000000..2db45c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -0,0 +1,62 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "l1d_cache_rd",
+ "BriefDescription": "L1D cache read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write ",
+ "EventCode": "0x41",
+ "EventName": "l1d_cache_wr",
+ "BriefDescription": "L1D cache write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "l1d_cache_refill_rd",
+ "BriefDescription": "L1D cache refill read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "l1d_cache_refill_wr",
+ "BriefDescription": "L1D refill write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "l1d_tlb_refill_rd",
+ "BriefDescription": "L1D tlb refill read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "l1d_tlb_refill_wr",
+ "BriefDescription": "L1D tlb refill write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "l1d_tlb_rd",
+ "BriefDescription": "L1D tlb read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "l1d_tlb_wr",
+ "BriefDescription": "L1D tlb write",
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "bus_access_rd",
+ "BriefDescription": "Bus access read",
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "bus_access_wr",
+ "BriefDescription": "Bus access write",
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index e61c9ca..952a05c 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000420f5160,v1,cavium,core
+0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
1.9.1
next prev parent reply other threads:[~2018-02-23 15:17 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-23 16:05 [PATCH v2 00/11] perf events patches for improved ARM64 support John Garry
2018-02-23 16:05 ` [PATCH v2 01/11] perf vendor events: drop incomplete multiple mapfile support John Garry
2018-02-23 16:05 ` [PATCH v2 02/11] perf vendor events: fix error code in json_events() John Garry
2018-02-23 16:05 ` [PATCH v2 03/11] perf vendor events: drop support for unused topic directories John Garry
2018-02-23 16:05 ` [PATCH v2 04/11] perf vendor events: add support for pmu events vendor subdirectory John Garry
2018-02-23 16:05 ` John Garry [this message]
2018-02-23 16:05 ` [PATCH v2 06/11] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory John Garry
2018-02-23 16:05 ` [PATCH v2 07/11] perf vendor events: add support for arch standard events John Garry
2018-02-27 9:48 ` Jiri Olsa
2018-02-27 9:58 ` John Garry
2018-02-23 16:05 ` [PATCH v2 08/11] perf vendor events arm64: add armv8-recommended.json John Garry
2018-02-23 16:05 ` [PATCH v2 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events John Garry
2018-02-23 16:05 ` [PATCH v2 10/11] perf vendor events arm64: fixup A53 " John Garry
2018-02-23 16:05 ` [PATCH v2 11/11] perf vendor events arm64: add HiSilicon hip08 JSON file John Garry
2018-02-27 9:50 ` [PATCH v2 00/11] perf events patches for improved ARM64 support Jiri Olsa
2018-02-27 10:03 ` John Garry
2018-03-02 8:24 ` John Garry
2018-03-02 8:45 ` Ganapatrao Kulkarni
2018-03-02 16:05 ` William Cohen
2018-03-02 16:35 ` Ganapatrao Kulkarni
2018-03-02 16:40 ` John Garry
2018-03-02 23:38 ` William Cohen
2018-03-05 11:24 ` John Garry
2018-03-05 15:39 ` William Cohen
2018-03-05 16:28 ` John Garry
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