linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Sricharan R <sricharan@codeaurora.org>
To: viresh.kumar@linaro.org, robh+dt@kernel.org,
	mark.rutland@arm.com, mturquette@baylibre.com,
	sboyd@codeaurora.org, linux@armlinux.org.uk,
	andy.gross@linaro.org, david.brown@linaro.org, rjw@rjwysocki.net,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-pm@vger.kernel.org, robh@kernel.org,
	sricharan@codeaurora.org, linux@arm.linux.org.uk
Subject: [PATCH v8 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu
Date: Tue, 27 Feb 2018 19:37:02 +0530	[thread overview]
Message-ID: <1519740422-3835-16-git-send-email-sricharan@codeaurora.org> (raw)
In-Reply-To: <1519740422-3835-1-git-send-email-sricharan@codeaurora.org>

In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 .../devicetree/bindings/cpufreq/krait-cpufreq.txt  | 363 +++++++++++++++++++++
 1 file changed, 363 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt

diff --git a/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
new file mode 100644
index 0000000..7b083c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
@@ -0,0 +1,363 @@
+QCOM KRAIT CPUFreq and OPP bindings
+===================================
+
+In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
+that has KRAIT processors the voltage value of each OPP varies
+based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
+defines the voltage and current value based on the speed/pvs/version
+combination blown in the efuse. The qcom-cpufreq driver reads the efuse
+value from the SoC to provide the OPP framework with required information.
+This is used to determine the voltage and current value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+--------------------
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+	- 'operating-points-v2-krait-cpu' for ipq8064, apq8064, msm8960,
+					      msm8974.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+		efuse registers that has information about the
+		speedbin/pvs/version that is used to select the right
+		voltage/current value pair. Note that the length field of the
+		nvmem-cell is used to differentiate between format 'A' or 'B'
+		efuse settings. len of '4' bytes is for format 'A' and '8'
+		bytes for format 'B'. Please refer the for nvmem-cells
+		bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+		and also examples below for both the cases.
+Example 1:
+---------
+
+/* For arch/arm/boot/dts/apq8064.dtsi --> format 'A' */
+cpus {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	CPU0: cpu@0 {
+		compatible = "qcom,krait";
+		enable-method = "qcom,kpss-acc-v1";
+		device_type = "cpu";
+		reg = <0>;
+		next-level-cache = <&L2>;
+		qcom,acc = <&acc0>;
+		qcom,saw = <&saw0>;
+		cpu-idle-states = <&CPU_SPC>;
+		operating-points-v2 = <&cpu_opp_table>;
+	};
+};
+
+qfprom: qfprom@700000 {
+	compatible      = "qcom,qfprom";
+	reg	      = <0x00700000 0x1000>;
+	#address-cells  = <1>;
+	#size-cells     = <1>;
+	ranges;
+	pvs_efuse: pvs {
+		reg = <0xc0 0x4>;
+	};
+};
+
+cpu_opp_table: opp-table {
+	compatible = "operating-points-v2-krait-cpu";
+	nvmem-cells = <&pvs_efuse>;
+
+		/*
+		 * Missing opp-shared property means CPUs switch DVFS states
+		 * independently.
+		 */
+
+		opp-918000000 {
+			opp-hz = /bits/ 64 <918000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1100000>;
+			opp-microvolt-speed0-pvs1-v0 = <1050000>;
+			opp-microvolt-speed0-pvs3-v0 = <1000000>;
+			opp-microvolt-speed0-pvs4-v0 = <975000>;
+			opp-microvolt-speed1-pvs0-v0 = <1025000>;
+			opp-microvolt-speed1-pvs1-v0 = <1000000>;
+			opp-microvolt-speed1-pvs2-v0 = <950000>;
+			opp-microvolt-speed1-pvs3-v0 = <925000>;
+			opp-microvolt-speed1-pvs4-v0 = <900000>;
+			opp-microvolt-speed1-pvs5-v0 = <900000>;
+			opp-microvolt-speed1-pvs6-v0 = <900000>;
+			opp-microvolt-speed2-pvs0-v0 = <975000>;
+			opp-microvolt-speed2-pvs1-v0 = <950000>;
+			opp-microvolt-speed2-pvs2-v0 = <925000>;
+			opp-microvolt-speed2-pvs3-v0 = <912500>;
+			opp-microvolt-speed2-pvs4-v0 = <900000>;
+			opp-microvolt-speed2-pvs5-v0 = <900000>;
+			opp-microvolt-speed2-pvs6-v0 = <900000>;
+			opp-microvolt-speed14-pvs0-v0 = <1025000>;
+			opp-microvolt-speed14-pvs1-v0 = <1000000>;
+			opp-microvolt-speed14-pvs2-v0 = <950000>;
+			opp-microvolt-speed14-pvs3-v0 = <925000>;
+			opp-microvolt-speed14-pvs4-v0 = <900000>;
+			opp-microvolt-speed14-pvs5-v0 = <900000>;
+			opp-microvolt-speed14-pvs6-v0 = <900000>;
+		};
+
+		opp-810000000 {
+			opp-hz = /bits/ 64 <810000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1075000>;
+			opp-microvolt-speed0-pvs1-v0 = <1025000>;
+			opp-microvolt-speed0-pvs3-v0 = <975000>;
+			opp-microvolt-speed0-pvs3-v0 = <962500>;
+			opp-microvolt-speed1-pvs0-v0 = <1000000>;
+			opp-microvolt-speed1-pvs1-v0 = <975000>;
+			opp-microvolt-speed1-pvs2-v0 = <937500>;
+			opp-microvolt-speed1-pvs3-v0 = <900000>;
+			opp-microvolt-speed1-pvs4-v0 = <887500>;
+			opp-microvolt-speed1-pvs5-v0 = <887500>;
+			opp-microvolt-speed1-pvs6-v0 = <887500>;
+			opp-microvolt-speed2-pvs0-v0 = <962500>;
+			opp-microvolt-speed2-pvs1-v0 = <937500>;
+			opp-microvolt-speed2-pvs2-v0 = <912500>;
+			opp-microvolt-speed2-pvs3-v0 = <900000>;
+			opp-microvolt-speed2-pvs4-v0 = <887500>;
+			opp-microvolt-speed2-pvs5-v0 = <887500>;
+			opp-microvolt-speed2-pvs6-v0 = <887500>;
+			opp-microvolt-speed14-pvs0-v0 = <1000000>;
+			opp-microvolt-speed14-pvs1-v0 = <975000>;
+			opp-microvolt-speed14-pvs2-v0 = <937500>;
+			opp-microvolt-speed14-pvs3-v0 = <900000>;
+			opp-microvolt-speed14-pvs4-v0 = <887500>;
+			opp-microvolt-speed14-pvs5-v0 = <887500>;
+			opp-microvolt-speed14-pvs6-v0 = <887500>;
+		};
+
+		opp-702000000 {
+			opp-hz = /bits/ 64 <702000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1025000>;
+			opp-microvolt-speed0-pvs1-v0 = <975000>;
+			opp-microvolt-speed0-pvs3-v0 = <925000>;
+			opp-microvolt-speed0-pvs3-v0 = <925000>;
+			opp-microvolt-speed1-pvs0-v0 = <962500>;
+			opp-microvolt-speed1-pvs1-v0 = <962500>;
+			opp-microvolt-speed1-pvs2-v0 = <925000>;
+			opp-microvolt-speed1-pvs3-v0 = <900000>;
+			opp-microvolt-speed1-pvs4-v0 = <875000>;
+			opp-microvolt-speed1-pvs5-v0 = <875000>;
+			opp-microvolt-speed1-pvs6-v0 = <875000>;
+			opp-microvolt-speed2-pvs0-v0 = <950000>;
+			opp-microvolt-speed2-pvs1-v0 = <925000>;
+			opp-microvolt-speed2-pvs2-v0 = <900000>;
+			opp-microvolt-speed2-pvs3-v0 = 900000>;
+			opp-microvolt-speed2-pvs4-v0 = <875000>;
+			opp-microvolt-speed2-pvs5-v0 = <875000>;
+			opp-microvolt-speed2-pvs6-v0 = <875000>;
+			opp-microvolt-speed14-pvs0-v0 = <962500>;
+			opp-microvolt-speed14-pvs1-v0 = <962500>;
+			opp-microvolt-speed14-pvs2-v0 = <925000>;
+			opp-microvolt-speed14-pvs3-v0 = <900000>;
+			opp-microvolt-speed14-pvs4-v0 = <875000>;
+			opp-microvolt-speed14-pvs5-v0 = <875000>;
+			opp-microvolt-speed14-pvs6-v0 = <875000>;
+		};
+
+		opp-594000000 {
+			opp-hz = /bits/ 64 <594000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1000000>;
+			opp-microvolt-speed0-pvs1-v0 = <950000>;
+			opp-microvolt-speed0-pvs3-v0 = <900000>;
+			opp-microvolt-speed0-pvs3-v0 = <900000>;
+			opp-microvolt-speed1-pvs0-v0 = <950000>;
+			opp-microvolt-speed1-pvs1-v0 = <950000>;
+			opp-microvolt-speed1-pvs2-v0 = <925000>;
+			opp-microvolt-speed1-pvs3-v0 = <900000>;
+			opp-microvolt-speed1-pvs4-v0 = <875000>;
+			opp-microvolt-speed1-pvs5-v0 = <875000>;
+			opp-microvolt-speed1-pvs6-v0 = <875000>;
+			opp-microvolt-speed2-pvs0-v0 = <950000>;
+			opp-microvolt-speed2-pvs1-v0 = <925000>;
+			opp-microvolt-speed2-pvs2-v0 = <900000>;
+			opp-microvolt-speed2-pvs3-v0 = <900000>;
+			opp-microvolt-speed2-pvs4-v0 = <875000>;
+			opp-microvolt-speed2-pvs5-v0 = <875000>;
+			opp-microvolt-speed2-pvs6-v0 = <875000>;
+			opp-microvolt-speed14-pvs0-v0 = <950000>;
+			opp-microvolt-speed14-pvs1-v0 = <950000>;
+			opp-microvolt-speed14-pvs2-v0 = <925000>;
+			opp-microvolt-speed14-pvs3-v0 = <900000>;
+			opp-microvolt-speed14-pvs4-v0 = <875000>;
+			opp-microvolt-speed14-pvs5-v0 = <875000>;
+			opp-microvolt-speed14-pvs6-v0 = <875000>;
+		};
+
+		opp-486000000 {
+			opp-hz = /bits/ 64 <486000000>;
+			opp-microvolt-speed0-pvs0-v0 = <975000>;
+			opp-microvolt-speed0-pvs1-v0 = <925000>;
+			opp-microvolt-speed0-pvs3-v0 = <875000>;
+			opp-microvolt-speed0-pvs3-v0 = <875000>;
+			opp-microvolt-speed1-pvs0-v0 = <950000>;
+			opp-microvolt-speed1-pvs1-v0 = <950000>;
+			opp-microvolt-speed1-pvs2-v0 = <925000>;
+			opp-microvolt-speed1-pvs3-v0 = <900000>;
+			opp-microvolt-speed1-pvs4-v0 = <875000>;
+			opp-microvolt-speed1-pvs5-v0 = <875000>;
+			opp-microvolt-speed1-pvs6-v0 = <875000>;
+			opp-microvolt-speed2-pvs0-v0 = <950000>;
+			opp-microvolt-speed2-pvs1-v0 = <925000>;
+			opp-microvolt-speed2-pvs2-v0 = <900000>;
+			opp-microvolt-speed2-pvs3-v0 = <900000>;
+			opp-microvolt-speed2-pvs4-v0 = <875000>;
+			opp-microvolt-speed2-pvs5-v0 = <875000>;
+			opp-microvolt-speed2-pvs6-v0 = <875000>;
+			opp-microvolt-speed14-pvs0-v0 = <950000>;
+			opp-microvolt-speed14-pvs1-v0 = <950000>;
+			opp-microvolt-speed14-pvs2-v0 = <925000>;
+			opp-microvolt-speed14-pvs3-v0 = <900000>;
+			opp-microvolt-speed14-pvs4-v0 = <875000>;
+			opp-microvolt-speed14-pvs5-v0 = <875000>;
+			opp-microvolt-speed14-pvs6-v0 = <875000>;
+		};
+
+		opp-384000000 {
+			opp-hz = /bits/ 64 <384000000>;
+			opp-microvolt-speed0-pvs0-v0 = <950000>;
+			opp-microvolt-speed0-pvs1-v0 = <900000>;
+			opp-microvolt-speed0-pvs3-v0 = <850000>;
+			opp-microvolt-speed0-pvs3-v0 = <850000>;
+			opp-microvolt-speed1-pvs0-v0 = <950000>;
+			opp-microvolt-speed1-pvs1-v0 = <950000>;
+			opp-microvolt-speed1-pvs2-v0 = <925000>;
+			opp-microvolt-speed1-pvs3-v0 = <900000>;
+			opp-microvolt-speed1-pvs4-v0 = <875000>;
+			opp-microvolt-speed1-pvs5-v0 = <875000>;
+			opp-microvolt-speed1-pvs6-v0 = <875000>;
+			opp-microvolt-speed2-pvs0-v0 = <950000>;
+			opp-microvolt-speed2-pvs1-v0 = <925000>;
+			opp-microvolt-speed2-pvs2-v0 = <900000>;
+			opp-microvolt-speed2-pvs3-v0 = <900000>;
+			opp-microvolt-speed2-pvs4-v0 = <875000>;
+			opp-microvolt-speed2-pvs5-v0 = <875000>;
+			opp-microvolt-speed2-pvs6-v0 = <875000>;
+			opp-microvolt-speed14-pvs0-v0 = <950000>;
+			opp-microvolt-speed14-pvs1-v0 = <950000>;
+			opp-microvolt-speed14-pvs2-v0 = <925000>;
+			opp-microvolt-speed14-pvs3-v0 = <900000>;
+			opp-microvolt-speed14-pvs4-v0 = <875000>;
+			opp-microvolt-speed14-pvs5-v0 = <875000>;
+			opp-microvolt-speed14-pvs6-v0 = <875000>;
+		};
+};
+
+EXAMPLE 2:
+---------
+/* For arch/arm/boot/dts/qcom-msm8974.dtsi--> format 'B' */
+
+qfprom: qfprom@700000 {
+	compatible      = "qcom,qfprom";
+	reg		= <0x00700000 0x1000>;
+	#address-cells	= <1>;
+	#size-cells	= <1>;
+	ranges;
+	pvs_efuse: pvs {
+		reg = <0xc0 0x8>;
+	};
+};
+
+cpu_opp_table: opp-table {
+	compatible = "operating-points-v2-krait-cpu";
+	nvmem-cells = <&pvs_efuse>;
+
+		/*
+		 * Missing opp-shared property means CPUs switch DVFS states
+		 * independently.
+		 */
+	opp-960000000 {
+		opp-hz = /bits/ 64 <960000000>;
+		opp-microvolt-speed0-pvs0-v0 = <915000>;
+		opp-microvolt-speed0-pvs1-v0 = <895000>;
+		opp-microvolt-speed0-pvs2-v0 = <875000>;
+		opp-microvolt-speed0-pvs3-v0 = <860000>;
+		opp-microvolt-speed0-pvs4-v0 = <850000>;
+		opp-microvolt-speed0-pvs5-v0 = <840000>;
+		opp-microvolt-speed0-pvs6-v0 = <830000>;
+		opp-microvolt-speed2-pvs0-v0 = <875000>;
+		opp-microvolt-speed2-pvs1-v0 = <860000>;
+		opp-microvolt-speed2-pvs2-v0 = <845000>;
+		opp-microvolt-speed2-pvs3-v0 = <830000>;
+		opp-microvolt-speed2-pvs4-v0 = <820000>;
+		opp-microvolt-speed2-pvs5-v0 = <810000>;
+		opp-microvolt-speed2-pvs6-v0 = <800000>;
+		opp-microvolt-speed1-pvs0-v0 = <840000>;
+		opp-microvolt-speed1-pvs1-v0 = <825000>;
+		opp-microvolt-speed1-pvs2-v0 = <810000>;
+		opp-microvolt-speed1-pvs3-v0 = <795000>;
+		opp-microvolt-speed1-pvs4-v0 = <785000>;
+		opp-microvolt-speed1-pvs5-v0 = <775000>;
+		opp-microvolt-speed1-pvs6-v0 = <765000>;
+
+		opp-microamp-speed0-pvs0-v0 = <252>;
+		opp-microamp-speed0-pvs1-v0 = <252>;
+		opp-microamp-speed0-pvs2-v0 = <252>;
+		opp-microamp-speed0-pvs3-v0 = <252>;
+		opp-microamp-speed0-pvs4-v0 = <252>;
+		opp-microamp-speed0-pvs5-v0 = <252>;
+		opp-microamp-speed0-pvs6-v0 = <252>;
+		opp-microamp-speed2-pvs0-v0 = <245>;
+		opp-microamp-speed2-pvs1-v0 = <245>;
+		opp-microamp-speed2-pvs2-v0 = <245>;
+		opp-microamp-speed2-pvs3-v0 = <245>;
+		opp-microamp-speed2-pvs4-v0 = <245>;
+		opp-microamp-speed2-pvs5-v0 = <245>;
+		opp-microamp-speed2-pvs6-v0 = <245>;
+		opp-microamp-speed1-pvs0-v0 = <242>;
+		opp-microamp-speed1-pvs1-v0 = <242>;
+		opp-microamp-speed1-pvs2-v0 = <242>;
+		opp-microamp-speed1-pvs3-v0 = <242>;
+		opp-microamp-speed1-pvs4-v0 = <242>;
+		opp-microamp-speed1-pvs5-v0 = <242>;
+		opp-microamp-speed1-pvs6-v0 = <242>;
+	};
+
+	opp-883200000 {
+		opp-hz = /bits/ 64 <883200000>;
+		opp-microvolt-speed0-pvs0-v0 = <900000>;
+		opp-microvolt-speed0-pvs1-v0 = <885000>;
+		opp-microvolt-speed0-pvs2-v0 = <865000>;
+		opp-microvolt-speed0-pvs3-v0 = <850000>;
+		opp-microvolt-speed0-pvs4-v0 = <840000>;
+		opp-microvolt-speed0-pvs5-v0 = <830000>;
+		opp-microvolt-speed0-pvs6-v0 = <820000>;
+		opp-microvolt-speed2-pvs0-v0 = <865000>;
+		opp-microvolt-speed2-pvs1-v0 = <850000>;
+		opp-microvolt-speed2-pvs2-v0 = <835000>;
+		opp-microvolt-speed2-pvs3-v0 = <820000>;
+		opp-microvolt-speed2-pvs4-v0 = <810000>;
+		opp-microvolt-speed2-pvs5-v0 = <800000>;
+		opp-microvolt-speed2-pvs6-v0 = <790000>;
+		opp-microvolt-speed1-pvs0-v0 = <830000>;
+		opp-microvolt-speed1-pvs1-v0 = <815000>;
+		opp-microvolt-speed1-pvs2-v0 = <800000>;
+		opp-microvolt-speed1-pvs3-v0 = <785000>;
+		opp-microvolt-speed1-pvs4-v0 = <775000>;
+		opp-microvolt-speed1-pvs5-v0 = <765000>;
+		opp-microvolt-speed1-pvs6-v0 = <755000>;
+
+		opp-microamp-speed0-pvs0-v0 = <229>;
+		opp-microamp-speed0-pvs1-v0 = <229>;
+		opp-microamp-speed0-pvs2-v0 = <229>;
+		opp-microamp-speed0-pvs3-v0 = <229>;
+		opp-microamp-speed0-pvs4-v0 = <229>;
+		opp-microamp-speed0-pvs5-v0 = <229>;
+		opp-microamp-speed0-pvs6-v0 = <229>;
+		opp-microamp-speed2-pvs0-v0 = <223>;
+		opp-microamp-speed2-pvs1-v0 = <223>;
+		opp-microamp-speed2-pvs2-v0 = <223>;
+		opp-microamp-speed2-pvs3-v0 = <223>;
+		opp-microamp-speed2-pvs4-v0 = <223>;
+		opp-microamp-speed2-pvs5-v0 = <223>;
+		opp-microamp-speed2-pvs6-v0 = <223>;
+		opp-microamp-speed1-pvs0-v0 = <221>;
+		opp-microamp-speed1-pvs1-v0 = <221>;
+		opp-microamp-speed1-pvs2-v0 = <221>;
+		opp-microamp-speed1-pvs3-v0 = <221>;
+		opp-microamp-speed1-pvs4-v0 = <221>;
+		opp-microamp-speed1-pvs5-v0 = <221>;
+		opp-microamp-speed1-pvs6-v0 = <221>;
+	};
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

  parent reply	other threads:[~2018-02-27 14:10 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-27 14:06 [PATCH v8 00/15] Krait clocks + Krait CPUfreq Sricharan R
2018-02-27 14:06 ` [PATCH v8 01/15] ARM: Add Krait L2 register accessor functions Sricharan R
2018-02-27 14:06 ` [PATCH v8 02/15] clk: mux: Split out register accessors for reuse Sricharan R
2018-02-27 14:06 ` [PATCH v8 03/15] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
2018-02-27 14:06 ` [PATCH v8 04/15] clk: qcom: Add HFPLL driver Sricharan R
2018-02-27 14:06 ` [PATCH v8 05/15] dt-bindings: clock: Document qcom,hfpll Sricharan R
2018-02-27 14:06 ` [PATCH v8 06/15] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
2018-02-27 14:06 ` [PATCH v8 07/15] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
2018-02-27 14:06 ` [PATCH v8 08/15] clk: qcom: Add support for Krait clocks Sricharan R
2018-02-27 14:06 ` [PATCH v8 09/15] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
2018-02-27 14:06 ` [PATCH v8 10/15] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R
2018-02-27 14:06 ` [PATCH v8 11/15] clk: qcom: Add Krait clock controller driver Sricharan R
2018-02-27 14:06 ` [PATCH v8 12/15] dt-bindings: clock: Document qcom,krait-cc Sricharan R
2018-02-27 14:07 ` [PATCH v8 13/15] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
2018-02-27 14:07 ` [PATCH v8 14/15] cpufreq: Add module to register cpufreq on Krait CPUs Sricharan R
2018-02-27 14:58   ` Gregory CLEMENT
2018-02-28  5:34     ` Sricharan R
2018-02-27 14:07 ` Sricharan R [this message]
2018-03-05 22:19   ` [PATCH v8 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu Rob Herring
2018-03-06  5:15     ` Sricharan R
2018-03-01 13:28 ` [PATCH v8 00/15] Krait clocks + Krait CPUfreq Linus Walleij
2018-03-02 14:12   ` Sricharan R

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1519740422-3835-16-git-send-email-sricharan@codeaurora.org \
    --to=sricharan@codeaurora.org \
    --cc=andy.gross@linaro.org \
    --cc=david.brown@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=linux-soc@vger.kernel.org \
    --cc=linux@arm.linux.org.uk \
    --cc=linux@armlinux.org.uk \
    --cc=mark.rutland@arm.com \
    --cc=mturquette@baylibre.com \
    --cc=rjw@rjwysocki.net \
    --cc=robh+dt@kernel.org \
    --cc=robh@kernel.org \
    --cc=sboyd@codeaurora.org \
    --cc=viresh.kumar@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).