From: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
To: Vinod Koul <vinod.koul@intel.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Dan Williams <dan.j.williams@intel.com>,
"M'boumba Cedric Madianga" <cedric.madianga@gmail.com>,
<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Subject: [PATCH v1 6/8] dmaengine: stm32-dma: properly mask irq bits
Date: Tue, 13 Mar 2018 17:42:05 +0100 [thread overview]
Message-ID: <1520959327-25760-7-git-send-email-pierre-yves.mordret@st.com> (raw)
In-Reply-To: <1520959327-25760-1-git-send-email-pierre-yves.mordret@st.com>
A single register of the controller holds the information for four dma
channels.
The functions stm32_dma_irq_status() don't mask the relevant bits after
the shift, thus adjacent channel's status is also reported in the returned
value.
Fixed by masking the value before returning it.
Similarly, the function stm32_dma_irq_clear() don't mask the input value
before shifting it, thus an incorrect input value could disable the
interrupts of adjacent channels.
Fixed by masking the input value before using it.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index f9d3c84..a11cbee 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -38,6 +38,10 @@
#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
+#define STM32_DMA_MASKI (STM32_DMA_TCI \
+ | STM32_DMA_TEI \
+ | STM32_DMA_DMEI \
+ | STM32_DMA_FEI)
/* DMA Stream x Configuration Register */
#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
@@ -404,7 +408,7 @@ static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
- return flags;
+ return flags & STM32_DMA_MASKI;
}
static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
@@ -419,6 +423,7 @@ static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
* If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
* If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
*/
+ flags &= STM32_DMA_MASKI;
dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
if (chan->id & 4)
--
2.7.4
next prev parent reply other threads:[~2018-03-13 16:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-13 16:41 [PATCH v1 0/8] Append several fixes and improvements in STM32 DMA Pierre-Yves MORDRET
2018-03-13 16:42 ` [PATCH v1 1/8] dt-bindings: stm32-dma: introduce DMA features bitfield Pierre-Yves MORDRET
2018-03-18 12:49 ` Rob Herring
2018-03-13 16:42 ` [PATCH v1 2/8] dmaengine: stm32-dma: threshold manages with bitfield feature Pierre-Yves MORDRET
2018-03-13 16:42 ` [PATCH v1 3/8] dmaengine: stm32-dma: Improve memory burst management Pierre-Yves MORDRET
2018-03-13 16:42 ` [PATCH v1 4/8] dmaengine: stm32-dma: fix DMA IRQ status handling Pierre-Yves MORDRET
2018-03-13 16:42 ` [PATCH v1 5/8] dmaengine: stm32-dma: fix max items per transfer Pierre-Yves MORDRET
2018-03-13 16:42 ` Pierre-Yves MORDRET [this message]
2018-03-13 16:42 ` [PATCH v1 7/8] dmaengine: stm32-dma: fix incomplete configuration in cyclic mode Pierre-Yves MORDRET
2018-03-13 16:42 ` [PATCH v1 8/8] dmaengine: stm32-dma: fix typo and reported checkpatch warnings Pierre-Yves MORDRET
2018-04-04 6:19 ` [PATCH v1 0/8] Append several fixes and improvements in STM32 DMA Vinod Koul
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