From: Yao Chen <chenyao11@huawei.com>
To: <songxiaowei@hisilicon.com>, <wangbinghui@hisilicon.com>,
<lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<xuwei5@hisilicon.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <catalin.marinas@arm.com>,
<will.deacon@arm.com>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>
Cc: <dimitrysh@google.com>, <guodong.xu@linaro.org>,
<chenyao11@huawei.com>, <suzhuangluan@hisilicon.com>,
<kongfei@hisilicon.com>
Subject: [PATCH v2 2/2] arm64: dts: hi3660: Add pcie msi interrupt attribute
Date: Wed, 9 May 2018 16:20:12 +0800 [thread overview]
Message-ID: <1525854012-24228-3-git-send-email-chenyao11@huawei.com> (raw)
In-Reply-To: <1525854012-24228-1-git-send-email-chenyao11@huawei.com>
Add pcie msi interrupt attribute for hi3660 SOC.
Signed-off-by: Yao Chen <chenyao11@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index ec3eb8e..2cef8f4 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -872,6 +872,8 @@
0x0 0x02000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
+ interrupts = <0 283 4>;
+ interrupt-names = "msi";
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1
&gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
--
1.9.1
prev parent reply other threads:[~2018-05-09 8:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-09 8:20 [PATCH v2 0/2] Add MSI support Yao Chen
2018-05-09 8:20 ` [PATCH v2 1/2] PCI: kirin: " Yao Chen
2018-05-10 14:04 ` Bjorn Helgaas
2018-05-11 8:30 ` chenyao (F)
2018-05-09 8:20 ` Yao Chen [this message]
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