From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752883AbeEKJQH (ORCPT ); Fri, 11 May 2018 05:16:07 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:56462 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752232AbeEKJQC (ORCPT ); Fri, 11 May 2018 05:16:02 -0400 From: Yao Chen To: , , , , , , , , , , , , CC: , , , , Subject: [PATCH v3 2/2] arm64: dts: hi3660: Add pcie msi interrupt attribute Date: Fri, 11 May 2018 17:15:49 +0800 Message-ID: <1526030149-23985-3-git-send-email-chenyao11@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526030149-23985-1-git-send-email-chenyao11@huawei.com> References: <1526030149-23985-1-git-send-email-chenyao11@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.143.148.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pcie msi interrupt attribute for hi3660 SOC. Signed-off-by: Yao Chen --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index ec3eb8e..2cef8f4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -872,6 +872,8 @@ 0x0 0x02000000>; num-lanes = <1>; #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, -- 1.9.1