From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id B92A2C07D5C for ; Thu, 14 Jun 2018 11:06:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 780D6208D7 for ; Thu, 14 Jun 2018 11:06:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 780D6208D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935854AbeFNLGc (ORCPT ); Thu, 14 Jun 2018 07:06:32 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:43898 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754860AbeFNLGa (ORCPT ); Thu, 14 Jun 2018 07:06:30 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie2.idc.renesas.com with ESMTP; 14 Jun 2018 20:06:29 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 07FC47E1AA; Thu, 14 Jun 2018 20:06:29 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.51,222,1526310000"; d="scan'208";a="282525973" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii1.idc.renesas.com with ESMTP; 14 Jun 2018 20:06:26 +0900 From: Michel Pollet To: linux-renesas-soc@vger.kernel.org, Simon Horman Cc: phil.edworthy@renesas.com, Michel Pollet , Michel Pollet , Linus Walleij , Rob Herring , Mark Rutland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] ARM: dts: Renesas RZN1D-DB Board: Add UART0 pinmux node Date: Thu, 14 Jun 2018 12:00:21 +0100 Message-Id: <1528974029-29617-6-git-send-email-michel.pollet@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528974029-29617-1-git-send-email-michel.pollet@bp.renesas.com> References: <1528974029-29617-1-git-send-email-michel.pollet@bp.renesas.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the necessary nodes to add pin configuration for the UART0 of that board. Signed-off-by: Michel Pollet --- arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 4e57ae2..039ec2e 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -8,6 +8,8 @@ /dts-v1/; +#include + #include "r9a06g032.dtsi" / { @@ -23,6 +25,17 @@ }; }; +&pinctrl { + pinsuart0: pinsuart0 { + renesas,rzn1-pinmux-ids = < + RZN1_MUX(103, UART0_I) /* UART0_TXD */ + RZN1_MUX(104, UART0_I) /* UART0_RXD */ + >; + }; +}; + &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinsuart0>; }; -- 2.7.4