From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id 37701C07D5C for ; Thu, 14 Jun 2018 14:47:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EBBB4208CB for ; Thu, 14 Jun 2018 14:47:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EBBB4208CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755449AbeFNOrI (ORCPT ); Thu, 14 Jun 2018 10:47:08 -0400 Received: from mga12.intel.com ([192.55.52.136]:50728 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755092AbeFNOrF (ORCPT ); Thu, 14 Jun 2018 10:47:05 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jun 2018 07:47:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,222,1526367600"; d="scan'208";a="66990540" Received: from 2b52.sc.intel.com (HELO [143.183.136.147]) ([143.183.136.147]) by orsmga002.jf.intel.com with ESMTP; 14 Jun 2018 07:47:03 -0700 Message-ID: <1528987432.13101.7.camel@2b52.sc.intel.com> Subject: Re: [PATCH 02/10] x86/cet: Introduce WRUSS instruction From: Yu-cheng Yu To: Balbir Singh Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , "H.J. Lu" , Vedvyas Shanbhogue , "Ravi V. Shankar" , Dave Hansen , Andy Lutomirski , Jonathan Corbet , Oleg Nesterov , Arnd Bergmann , Mike Kravetz Date: Thu, 14 Jun 2018 07:43:52 -0700 In-Reply-To: References: <20180607143807.3611-1-yu-cheng.yu@intel.com> <20180607143807.3611-3-yu-cheng.yu@intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2018-06-14 at 11:30 +1000, Balbir Singh wrote: > On Thu, 2018-06-07 at 07:37 -0700, Yu-cheng Yu wrote: > > WRUSS is a new kernel-mode instruction but writes directly > > to user shadow stack memory. This is used to construct > > a return address on the shadow stack for the signal > > handler. > > > > This instruction can fault if the user shadow stack is > > invalid shadow stack memory. In that case, the kernel does > > fixup. > > > > Signed-off-by: Yu-cheng Yu > > --- > > arch/x86/include/asm/special_insns.h | 44 +++++++++++++++++++++++++++ > > arch/x86/lib/x86-opcode-map.txt | 2 +- > > arch/x86/mm/fault.c | 13 +++++++- > > tools/objtool/arch/x86/lib/x86-opcode-map.txt | 2 +- > > 4 files changed, 58 insertions(+), 3 deletions(-) > > > > diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h > > index 317fc59b512c..8ce532fcc171 100644 > > --- a/arch/x86/include/asm/special_insns.h > > +++ b/arch/x86/include/asm/special_insns.h > > @@ -237,6 +237,50 @@ static inline void clwb(volatile void *__p) > > : [pax] "a" (p)); > > } > > > > +#ifdef CONFIG_X86_INTEL_CET > > + > > +#if defined(CONFIG_IA32_EMULATION) || defined(CONFIG_X86_X32) > > +static inline int write_user_shstk_32(unsigned long addr, unsigned int val) > > +{ > > + int err; > > + > > + asm volatile("1:.byte 0x66, 0x0f, 0x38, 0xf5, 0x37\n" > > It would nice to use something like ASM_WRUSS/Q like ASM_CLAC/ASM_STAC. > Is the 0x37 spurious? I don't see addr/val being used in the instructions > either. > Yes, this is being revised. We are going to require a GCC and binutils that support CET. I will put in the WRUSS instruction, no '.byte' any more. Yu-cheng